{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T14:28:20Z","timestamp":1774448900033,"version":"3.50.1"},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":88,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2000,1]]},"abstract":"<jats:p>A method of a self\u2010checking synchronous Finite State Machine (FSM) network design\nwith low overhead is developed. Checkers are used only for FSMs, which output lines\nare at the same time output lines of the network. The checkers observe output lines of\nthese FSMs. The method is based on reducing the problem to a self\u2010checking synchronous\nFSM design. The latter is provided by applying a special description of FSM\nnamely, so\u2010called unate Programmable Logic Array (PLA<jats:sup>u<\/jats:sup>) description. Single stuck\u2010at\nfault on the FSM poles and gate poles are considered. PLA<jats:sup>u<\/jats:sup> realization of FSM allows a\nfactorized or multilevel logic synthesis. They both provide a unidirectional manifestation\nof the above mentioned faults on the output lines of the corresponding FSMs. This\nrealization also gives rise to a transparency of each component FSM of the network for\nthe faults. PLA<jats:sup>u<\/jats:sup> realization is derived from the State Transition Graph (STG) description\nof FSMs with using the <jats:italic>m<\/jats:italic>\u2010out\u2010of\u2010<jats:italic>n<\/jats:italic> encoding of its states and insignificant\nexpanding the products of STG. The problem of replacing an arbitrary synchronous\nFSM network for the self\u2010checking one with low overhead is discussed.<\/jats:p>","DOI":"10.1155\/2000\/46578","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:57Z","timestamp":1190120337000},"page":"47-58","update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":41,"title":["Self\u2010checking Synchronous FSM Network Design with Low Overhead"],"prefix":"10.1155","volume":"11","author":[{"given":"A. Yu.","family":"Matrosova","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"I.","family":"Levin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S. A.","family":"Ostanin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,10,5]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2000\/046578.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/2000\/046578.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2000\/46578","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T05:25:35Z","timestamp":1723094735000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2000\/46578"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,10,5]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2000,1]]}},"alternative-id":["10.1155\/2000\/46578"],"URL":"https:\/\/doi.org\/10.1155\/2000\/46578","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"value":"1065-514X","type":"print"},{"value":"1563-5171","type":"electronic"}],"subject":[],"published":{"date-parts":[[1999,10,5]]},"assertion":[{"value":"1999-04-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-10-05","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-10-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}