{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:40:01Z","timestamp":1723203601523},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":92,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2000,1]]},"abstract":"<jats:p>In high\u2010speed digital systems and high\u2010resolution display devices, the jitter effect of\nphase\u2010locked loops (PLL) limits the system performance. Power supply noise coupling is\none of the major causes of PLL jitter problems, especially with mixed\u2010signal systems.\nThe paper presents a targeted 5.0V 500 MHz PLL which is implemented by a 0.6 um\n1P3M digital CMOS technology. The features of the proposed design include a load\u2010optimized\n3\u2010stage VCO, a frequency limiter RC circuit, and a ratioed VCO controlling\ncurrent mirror. The jitter, thus, is reduced to 72.693 ps at 600 MHz at the presence of\nsupply noise, while the sensitivity is limited to 286.6 ps\/V. This high\u2010noise immunity\ndesign allows that the PLL can be integrated with digital circuits.<\/jats:p>","DOI":"10.1155\/2000\/52658","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:57Z","timestamp":1190120337000},"page":"107-113","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Practical Load\u2010optimized VCO Design for Low\u2010jitter 5V 500 MHz Digital Phase\u2010locked Loop"],"prefix":"10.1155","volume":"11","author":[{"given":"Chua-Chin","family":"Wang","sequence":"first","affiliation":[]},{"given":"Yu-Tsun","family":"Chien","sequence":"additional","affiliation":[]},{"given":"Ying-Pei","family":"Chen","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1999,10]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2000\/052658.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2000\/52658","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:24:00Z","timestamp":1723202640000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2000\/52658"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,10]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2000,1]]}},"alternative-id":["10.1155\/2000\/52658"],"URL":"https:\/\/doi.org\/10.1155\/2000\/52658","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,10]]},"assertion":[{"value":"1999-06-05","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-10-01","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-10-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}