{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:40:02Z","timestamp":1723070402075},"reference-count":0,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":31,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2000,1]]},"abstract":"<jats:p>Mathematically the most difficult partitioning problem\u2013packaging\u2013is being considered.\nIts purpose is to minimize a number of partitions and to satisfy the constraints on\nthe number of constituent elements and external nets. To solve the problem, the Optimal\nCircuit Reduction Method, suggested by R. Bazylevych is being used. The optimal\nreduction tree to reflect the hierarchical entrance of smaller clusters into bigger ones is\nbeing built for the first step. At the second step we select one or more tree vertices which\nbetter meet the given constraints and are the first partitions generated from. After\ncreating every new partition we eliminate its elements from the circuit and repeat the\nprocedure to complete all partitions. During the last stage optimization strategies to\nexchange some elements between the partitions are being used. Better or equivalent\nresults among known tests confirm the effectiveness of this method.<\/jats:p>","DOI":"10.1155\/2000\/58485","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:57Z","timestamp":1190120337000},"page":"237-248","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method"],"prefix":"10.1155","volume":"11","author":[{"given":"R. P.","family":"Bazylevych","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R. A.","family":"Melnyk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"O. G.","family":"Rybak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,12]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2000\/058485.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2000\/58485","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:19:40Z","timestamp":1723069180000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2000\/58485"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,12]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2000,1]]}},"alternative-id":["10.1155\/2000\/58485"],"URL":"https:\/\/doi.org\/10.1155\/2000\/58485","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,12]]},"assertion":[{"value":"1999-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-12-01","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-12-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}