{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:40:01Z","timestamp":1723203601822},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":80,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2000,1]]},"abstract":"<jats:p>Recently a multiple\u2010sequence test generator was presented based on two\u2010dimensional\nlinear feedback shift registers (2\u2010D LFSR). This generator can generate a set of precomputed\ntest vectors obtained by an ATPG tool for detecting random\u2010pattern\u2010resistant\nfaults and particular hard\u2010to\u2010detect faults. In addition, it can generate better random\npatterns than a conventional LFSR. In this paper we describe an optimized BIST scheme\nwhich has a configurable 2\u2010D LFSR structure. Starting from a set of stuck\u2010at faults and\na corresponding set of test vectors detecting these faults, the corresponding test pattern\ngenerator is determined automatically. A synthesis procedure of designing this test\ngenerator is presented. Experimental results show that the hardware overhead is considerably\nreduced compared with 2\u2010D LFSR generators.<\/jats:p>","DOI":"10.1155\/2000\/60904","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:57Z","timestamp":1190120337000},"page":"149-159","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Configurable 2\u2010D Linear Feedback Shift Registers for VLSI Built\u2010in Self\u2010test Designs"],"prefix":"10.1155","volume":"11","author":[{"given":"Chien-In Henry","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yingjie","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,10,13]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2000\/060904.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2000\/60904","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:24:02Z","timestamp":1723202642000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2000\/60904"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,10,13]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2000,1]]}},"alternative-id":["10.1155\/2000\/60904"],"URL":"https:\/\/doi.org\/10.1155\/2000\/60904","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,10,13]]},"assertion":[{"value":"1999-05-20","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-10-13","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-10-13","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}