{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:40:01Z","timestamp":1723203601949},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":99,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2000,1]]},"abstract":"<jats:p>A high speed 64b\/32b integer divider employing digit\u2010recurrence division method and\nthe on\u2010the\u2010fly conversion algorithm, wherein a fast normalizer is included, which is used\nas the pre\u2010processor of the proposed integer divider. For the sake of enhancing\nthroughput rate, the proposed divider uses a mixed radix\u20108\/4\/2 division instead of the\ntraditional radix\u20102 division. On\u2010the\u2010fly remainder adjustment is also realized in the\nconverter module of the divider. The entire design is written in Verilog HDL (hardware\ndescription language) employing COMPASS 0.6 \u03bcm 1P3M cell library (V3.0), and then\nsynthesized by SYNOPSYS. The simulation results indicate that our design is a better\noption than the existing long divider designs.<\/jats:p>","DOI":"10.1155\/2000\/69148","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:57Z","timestamp":1190120337000},"page":"331-338","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Design and Analysis of Radix\u20108\/4\/2 64b\/32b Integer Divider Using COMPASS Cell Library"],"prefix":"10.1155","volume":"11","author":[{"given":"Chua-Chin","family":"Wang","sequence":"first","affiliation":[]},{"given":"Chenn-Jung","family":"Huang","sequence":"additional","affiliation":[]},{"given":"I-Yen","family":"Chang","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1999,9,24]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2000\/069148.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2000\/69148","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:24:31Z","timestamp":1723202671000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2000\/69148"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,9,24]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2000,1]]}},"alternative-id":["10.1155\/2000\/69148"],"URL":"https:\/\/doi.org\/10.1155\/2000\/69148","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,9,24]]},"assertion":[{"value":"1999-06-05","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-09-24","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-09-24","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}