{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:40:01Z","timestamp":1723203601815},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":113,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2000,1]]},"abstract":"<jats:p>Inner product calculations are often required in digital neural computing. The critical\npath of the inner product of two binary vectors is the carry propagation delay generated\nfrom individual product terms. In this work, two architectures to arrange digital ratioed\ncompressors are presented to reduce the carry propagation delay in the critical path.\nBesides, the carry propagation delay estimation of these compressor building blocks is\nderived and compared. The theoretical analysis and Verilog simulation both indicate\nthat one of the compressor building blocks we present here might offer a sub\u2010optimal\nsolution for the basic building blocks used in digital hardware realization of the inner\nproduct computation.<\/jats:p>","DOI":"10.1155\/2000\/72812","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:57Z","timestamp":1190120337000},"page":"353-361","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Design and Analysis of Digital Ratioed Compressors for Inner Product Processing"],"prefix":"10.1155","volume":"11","author":[{"given":"Chua-Chin","family":"Wang","sequence":"first","affiliation":[]},{"given":"Chenn-Jung","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Po-Ming","family":"Lee","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[1999,9,10]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2000\/072812.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2000\/72812","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T11:24:25Z","timestamp":1723202665000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2000\/72812"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,9,10]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2000,1]]}},"alternative-id":["10.1155\/2000\/72812"],"URL":"https:\/\/doi.org\/10.1155\/2000\/72812","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,9,10]]},"assertion":[{"value":"1999-06-05","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-09-10","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-09-10","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}