{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:10:02Z","timestamp":1723090202586},"reference-count":0,"publisher":"Wiley","issue":"3","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":92,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2000,1]]},"abstract":"<jats:p>Dynamic reconfigurable field\u2010programmable logic arrays (FPGAs) are receiving notable\nattention because of their much shorter reconfiguration time as compared with\ntraditional FPGAs. The short reconfiguration time is vital to applications such as\nreconfigurable computing and emulation. We show in this paper that testing and\ndiagnosis of the FPGA also can take advantage of its dynamic reconfigurability. We\nfirst propose an efficient methodology for testing the interconnects of the FPGA, then\npresent several universal test and diagnosis approaches which cover all functional units\nof the FPGA. Experimental results show that our approach significantly reduces the\ntesting time, without additional cost for diagnosis.<\/jats:p>","DOI":"10.1155\/2000\/79281","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:58:37Z","timestamp":1190120317000},"page":"321-333","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Testing and Diagnosing Dynamic Reconfigurable FPGA"],"prefix":"10.1155","volume":"10","author":[{"given":"Chi-Feng","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cheng-Wen","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,10]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2000\/079281.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2000\/79281","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T03:28:02Z","timestamp":1723087682000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2000\/79281"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,10]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2000,1]]}},"alternative-id":["10.1155\/2000\/79281"],"URL":"https:\/\/doi.org\/10.1155\/2000\/79281","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,10]]},"assertion":[{"value":"1999-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-10-01","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-10-01","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}