{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:40:02Z","timestamp":1723092002045},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2001,1]]},"abstract":"<jats:p>Testing and power consumption are becoming two critical issues in VLSI design due to\nthe growing complexity of VLSI circuits and remarkable success and growth of low\npower applications (<jats:italic>viz<\/jats:italic>. portable consumer electronics and space applications). On chip\nBuilt In Self Test (BIST) is a cost\u2010effective test methodology for highly complex VLSI\ndevices like Systems On Chip. This paper deals with cost\u2010effective Test Pattern Generation\n(TPG) schemes in BIST. We present a novel methodology based on the use of\na suitable Linear Feedback Shift Register (LFSR) which cycles through the required\nsequences (test vectors) aiming at a desired fault coverage causing minimum circuit\ntoggling and hence low power consumption while testing. The proposed technique uses\ncircuit simulation data for modeling. We show how to identify the LFSR using graph\ntheory techniques and compute its feedback coefficients (<jats:italic>i.e.<\/jats:italic>, its characteristic\npolynomial) for realization of a Test Pattern Generator.<\/jats:p>","DOI":"10.1155\/2001\/45324","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:59:02Z","timestamp":1190120342000},"page":"551-562","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["An Efficient Test Pattern Generation Scheme for an On Chip BIST"],"prefix":"10.1155","volume":"12","author":[{"given":"B. K. S. V. L.","family":"Varaprasad","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L. M.","family":"Patnaik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H. S.","family":"Jamadagni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V. K.","family":"Agrawal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2000,9,11]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2001\/045324.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2001\/45324","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:23:22Z","timestamp":1723091002000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2001\/45324"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,9,11]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2001,1]]}},"alternative-id":["10.1155\/2001\/45324"],"URL":"https:\/\/doi.org\/10.1155\/2001\/45324","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2000,9,11]]},"assertion":[{"value":"1999-08-15","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2000-09-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}