{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:40:01Z","timestamp":1723070401480},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":79,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2001,1]]},"abstract":"<jats:p>In this paper, we first employ an efficient approach to reduce the time to construct a\ncodeword. With this codeword, a novel VLSI architecture is proposed to realize highspeed\nVariable Length Coding (VLC). In order to combine with other circuits using cell\u2010based\ndesign, we adopt distributed logic rather than memory devices (ROM, PLA) for\nthe implementation. In this architecture, the VLC coding scheme is partitioned into two\nparts, one is the codeword length and order index for bit control, another is the\ncodeword bank for actual codeword generation. The advantage is that the circuit size of\nthe proposed method can be reduced, where the transistor count of proposed method is\nonly 1\/2 and 1\/4 of that of ROM\u2010 based and PLA\u2010based in average, respectively.<\/jats:p>","DOI":"10.1155\/2001\/53729","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:59:02Z","timestamp":1190120342000},"page":"61-68","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Size\u2010optimization Design for Variable Length Coding Using Distributed Logic"],"prefix":"10.1155","volume":"12","author":[{"given":"Shih-Chang","family":"Hsia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chien-Cheng","family":"Tseng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,10,14]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2001\/053729.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2001\/53729","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:23:20Z","timestamp":1723069400000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2001\/53729"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,10,14]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2001,1]]}},"alternative-id":["10.1155\/2001\/53729"],"URL":"https:\/\/doi.org\/10.1155\/2001\/53729","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,10,14]]},"assertion":[{"value":"1999-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-10-14","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}