{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T16:53:52Z","timestamp":1742403232043},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2001,1]]},"abstract":"<jats:p>Multimedia algorithms deal with enormous amounts of data transfers and storage,\nresulting in huge bandwidth requirements at the off\u2010chip memory and system bus level.\nAs a result the related energy consumption becomes critical. Even for execution time the\nbottleneck can shift from the CPU to the external bus load. This paper demonstrates\na systematic software approach to reduce this system bus load. It consists of source\u2010to\u2010source\ncode transformations, that have to be applied before the conventional ILP\ncompilation. To illustrate this we use a cavity detection algorithm for medical imaging,\nthat is mapped on an Intel Pentium\u00ae II processor.<\/jats:p>","DOI":"10.1155\/2001\/61965","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:59:02Z","timestamp":1190120342000},"page":"101-111","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms"],"prefix":"10.1155","volume":"12","author":[{"given":"Koen","family":"Danckaert","sequence":"first","affiliation":[]},{"given":"Chidamber","family":"Kulkarni","sequence":"additional","affiliation":[]},{"given":"Francky","family":"Catthoor","sequence":"additional","affiliation":[]},{"given":"Hugo","family":"De Man","sequence":"additional","affiliation":[]},{"given":"Vivek","family":"Tiwari","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2000,8,3]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2001\/061965.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2001\/61965","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:58:12Z","timestamp":1723197492000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2001\/61965"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,8,3]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2001,1]]}},"alternative-id":["10.1155\/2001\/61965"],"URL":"https:\/\/doi.org\/10.1155\/2001\/61965","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2000,8,3]]},"assertion":[{"value":"2000-06-20","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2000-08-03","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}