{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,12]],"date-time":"2025-04-12T05:08:35Z","timestamp":1744434515160},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2001,1]]},"abstract":"<jats:p>We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS)\ntechniques for power optimizations. We introduce a fast heuristic for choosing gates for\nsizing and voltage scaling such that the total power is minimized under delay constraints.\nWe also use a more accurate estimate for determining the power dissipation of\nthe circuit by taking into account the short circuit power along with the dynamic power.\nA better model of the short circuit power is used which takes into account the load\ncapacitance of the gates. Our results show that the combination of VS and GS perform\nbetter than the techniques applied in isolation. An average power reduction of 73% is\nobtained when decisions are taken assuming dynamic power only. In contrast, average\npower reduction is 77% when decisons include the short circuit power dissipation.<\/jats:p>","DOI":"10.1155\/2001\/65638","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:59:02Z","timestamp":1190120342000},"page":"125-138","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Power Optimization of Delay Constrained Circuits"],"prefix":"10.1155","volume":"12","author":[{"given":"Anshuman","family":"Nayak","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Malay","family":"Haldar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Prith","family":"Banerjee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chunhong","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Majid","family":"Sarrafzadeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2000,8,3]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2001\/065638.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2001\/65638","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:58:15Z","timestamp":1723197495000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2001\/65638"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,8,3]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2001,1]]}},"alternative-id":["10.1155\/2001\/65638"],"URL":"https:\/\/doi.org\/10.1155\/2001\/65638","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2000,8,3]]},"assertion":[{"value":"2000-06-20","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2000-08-03","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}