{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:40:02Z","timestamp":1723092002384},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2001,1]]},"abstract":"<jats:p>We present novel test set encoding and pattern decompression methods for core\u2010based\nsystems. These are based on the use of twisted\u2010ring counters and offer a number of\nimportant advantages\u2013significant test compression (over 10X in many cases), less tester\nmemory and reduced testing time, the ability to use a slow tester without compromising\ntest quality or testing time, and no performance degradation for the core under test.\nSurprisingly, the encoded test sets obtained from partially\u2010specified test sets (test cubes)\nare often smaller than the compacted test sets generated by automatic test pattern\ngeneration programs. Moreover, a large number of patterns are applied test\u2010per\u2010clock to\ncores, thereby increasing the likelihood of detecting non\u2010modeled faults. Experimental\nresults for the ISCAS benchmark circuits demonstrate that the proposed test\narchitecture offers an attractive solution to the problem of achieving high test quality\nand low testing time with relatively slower, less expensive testers.<\/jats:p>","DOI":"10.1155\/2001\/75139","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:59:02Z","timestamp":1190120342000},"page":"475-486","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Efficient Test Application for Core\u2010Based Systems Using Twisted\u2010Ring Counters"],"prefix":"10.1155","volume":"12","author":[{"given":"Anshuman","family":"Chandra","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark C.","family":"Hansen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2000,9,11]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2001\/075139.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2001\/75139","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:23:17Z","timestamp":1723090997000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2001\/75139"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,9,11]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2001,1]]}},"alternative-id":["10.1155\/2001\/75139"],"URL":"https:\/\/doi.org\/10.1155\/2001\/75139","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2000,9,11]]},"assertion":[{"value":"1999-08-15","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2000-09-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}