{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,21]],"date-time":"2025-04-21T04:26:04Z","timestamp":1745209564052},"reference-count":0,"publisher":"Wiley","issue":"2","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2001,1]]},"abstract":"<jats:p>Power constraints are becoming a critical design issue in the field of portable\nmicroprocessor systems. The impact of software on overall system power is becoming\nincreasingly important as more and more digital applications are implemented as\nembedded systems, part of which are hardware (ASICs) and part software in which a\nspecific application is executed on a processor. In this paper, a data\u2010dependent\ninstruction\u2010level power analysis model is presented. It is compared with the average cost\nmodel proposed by Tiwari <jats:italic>et al<\/jats:italic>. [1] in both estimation accuracy and characterisation\ntime. The data\u2010dependent model can be generalised to be applied to generic RISC\nprocessor. Application of the data\u2010dependent model we propose sensibly reduces errors\nin estimating software power consumption per clock cycle which is lower than 10%, in\nthe case of the ST20\u2010C2P core.<\/jats:p>","DOI":"10.1155\/2001\/82129","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:59:02Z","timestamp":1190120342000},"page":"245-273","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["An Instruction\u2010Level Power Analysis Model with Data Dependency"],"prefix":"10.1155","volume":"12","author":[{"given":"Giuseppe","family":"Ascia","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vincenzo","family":"Catania","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maurizio","family":"Palesi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Sarta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2000,8,3]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2001\/082129.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2001\/82129","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,9]],"date-time":"2024-08-09T09:58:16Z","timestamp":1723197496000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2001\/82129"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,8,3]]},"references-count":0,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2001,1]]}},"alternative-id":["10.1155\/2001\/82129"],"URL":"https:\/\/doi.org\/10.1155\/2001\/82129","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2000,8,3]]},"assertion":[{"value":"2000-06-20","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2000-08-03","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}