{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:40:02Z","timestamp":1723092002063},"reference-count":0,"publisher":"Wiley","issue":"4","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2001,1]]},"abstract":"<jats:p>Generally, there exist random\u2010pattern resistant faults that result in the poor fault\ncoverage in Build\u2010In Self\u2010Testing (BIST) scheme. In this paper, we propose a method to\nenhance the random pattern testability by a circuit restructuring technique, called <jats:italic>circuit\nrewiring<\/jats:italic>. The basic idea of rewiring is to replace a wire by another wire with the circuit\nfunctionality remaining unchanged. For two types of rewiring, fanin rewiring and\nfanout rewiring, we first analyze the testability change for each type of wire replacement.\nBased on the analysis, an efficient algorithm is given to enhance circuit testability. For a\npoor observability node, we try to increase its observability by adding an additional\nfanout to the node and removing an alternative wire whose source node has relatively\ngood observability. The technique does not introduce any hardware overhead and\nperformance degradation since a wire addition is followed immediately by another wire\nremoval. Thus, it is basically cost\u2010free when compared to other testability enhancement\ntechniques.<\/jats:p>","DOI":"10.1155\/2001\/87048","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:59:02Z","timestamp":1190120342000},"page":"537-549","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Random Pattern Testability Enhancement by Circuit Rewiring"],"prefix":"10.1155","volume":"12","author":[{"given":"Shih-Chieh","family":"Chang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kwen-Yo","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ching-Hwa","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wen-Ben","family":"Jone","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sunil R.","family":"Das","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2000,9,11]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2001\/087048.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2001\/87048","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,8]],"date-time":"2024-08-08T04:23:25Z","timestamp":1723091005000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2001\/87048"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,9,11]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2001,1]]}},"alternative-id":["10.1155\/2001\/87048"],"URL":"https:\/\/doi.org\/10.1155\/2001\/87048","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2000,9,11]]},"assertion":[{"value":"1999-08-15","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2000-09-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}