{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:40:01Z","timestamp":1723070401439},"reference-count":0,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2000,1,1]],"date-time":"2000-01-01T00:00:00Z","timestamp":946684800000},"content-version":"vor","delay-in-days":29,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2001,1]]},"abstract":"<jats:p>Search based placement of modules is an important problem in VLSI design. It is always\ndesired that the search should converge quickly to a high quality solution. This paper\npresents a tabu search based optimization technique to place modules on a regular two\u2010dimensional\narray. The goal of the technique is to speed up the placement process. The\ntechnique is based on a two\u2010step placement strategy. The first step is targeted toward\nimproving circuit routability and the second step addresses circuit performance. The\ntechnique is demonstrated through placement of several benchmark circuits on\nacademic as well as commercial FPGAs. Results are compared to placements generated\nby commercial CAE tools and published simulated annealing based techniques. The\ntabu search technique compares favorably to published simulated annealing based\ntechniques, and it demonstrates an average execution time speedup of 20 with no impact\non quality of results when compared to commercial tools.<\/jats:p>","DOI":"10.1155\/2001\/92781","type":"journal-article","created":{"date-parts":[[2007,9,18]],"date-time":"2007-09-18T12:59:02Z","timestamp":1190120342000},"page":"13-23","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Two\u2010dimensional Placement Using Tabu Search"],"prefix":"10.1155","volume":"12","author":[{"given":"John M.","family":"Emmert","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dinesh K.","family":"Bhatia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[1999,12,3]]},"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2001\/092781.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2001\/92781","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,7]],"date-time":"2024-08-07T22:23:26Z","timestamp":1723069406000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2001\/92781"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,12,3]]},"references-count":0,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2001,1]]}},"alternative-id":["10.1155\/2001\/92781"],"URL":"https:\/\/doi.org\/10.1155\/2001\/92781","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[1999,12,3]]},"assertion":[{"value":"1999-11-17","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"1999-12-03","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}