{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T04:06:30Z","timestamp":1648785990725},"reference-count":4,"publisher":"Hindawi Limited","license":[{"start":{"date-parts":[[2007,7,10]],"date-time":"2007-07-10T00:00:00Z","timestamp":1184025600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2007,7,10]]},"abstract":"<jats:p>This paper presents the necessary steps to modify the implementation of the \n\t\t\tSPARCV8 architecture to enhance it with multimedia-oriented instructions. The purpose\n\t\t\t is improving video compression performance without designing dedicated\ncoprocessors. We investigate the complexity of modifying a standard processor instruction \nset and show that, although not trivial, this is feasible in a few weeks. We\nimplemented 12 new instructions and use some of them to optimize the computation\nof a demanding step of the MPEG encoding. The result is a performance increase of\n 67% in the execution of a part of this algorithm, allowing us to expect a 30% speedup in \n the execution of an MPEG video compression. The area increase of the integer unit is about \n 18% and the clock frequency is not significantly modified in an LEON-2 implementing 6 among \n 12 of the new instructions.<\/jats:p>","DOI":"10.1155\/2007\/28686","type":"journal-article","created":{"date-parts":[[2007,7,15]],"date-time":"2007-07-15T11:19:17Z","timestamp":1184498357000},"page":"1-10","source":"Crossref","is-referenced-by-count":2,"title":["On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration"],"prefix":"10.1155","volume":"2007","author":[{"given":"P.","family":"Guironnet de Massas","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Amblard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"P\u00e9trot","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"98","reference":[{"key":"1","volume-title":"The Complete Guide to MMX Technology","year":"1997"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/40.526921"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.43"},{"issue":"2","key":"22","first-page":"226","volume":"9","year":"1960","journal-title":"IRE Transactions on Electronic Computers"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/028686.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/028686.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,8]],"date-time":"2020-12-08T20:06:28Z","timestamp":1607457988000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2007\/028686\/abs\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,7,10]]},"references-count":4,"alternative-id":["028686","28686"],"URL":"https:\/\/doi.org\/10.1155\/2007\/28686","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"value":"1065-514X","type":"print"},{"value":"1563-5171","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,7,10]]}}}