{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,1,8]],"date-time":"2023-01-08T15:48:46Z","timestamp":1673192926124},"reference-count":8,"publisher":"Hindawi Limited","license":[{"start":{"date-parts":[[2007,6,21]],"date-time":"2007-06-21T00:00:00Z","timestamp":1182384000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2007,6,21]]},"abstract":"<jats:p>In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential\n\t elements into the global interconnect lines has been proposed to support multicycle \n\t communication\u2014a concept known as interconnect pipelining. The design targets \n\t of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and \n\t less delay cycles. This paper presents an in-depth analysis of the reliability in terms of bit error\n\t  rate (BER) and the power consumption of wire-pipelining scheme. In this analysis,\n\t   the dependencies of power consumption and BER on the number of inserted flip-flops, \n\t   and the size of repeaters are illustrated. To trade off the design targets (wire delay, BER,\n\t    and power consumption), a methodology is developed to optimize the repeater size and\n\t     the number of flip-flops inserted which maximize a user-specified figure of merit. \n\t     The methodology is demonstrated by calculating optimal solutions for interconnect pipelining \n\t     for some International Technology Roadmap for Semiconductor technology nodes.<\/jats:p>","DOI":"10.1155\/2007\/42829","type":"journal-article","created":{"date-parts":[[2007,6,28]],"date-time":"2007-06-28T12:27:49Z","timestamp":1183033669000},"page":"1-8","source":"Crossref","is-referenced-by-count":2,"title":["Power Consumption and BER of Flip-Flop Inserted Global Interconnect"],"prefix":"10.1155","volume":"2007","author":[{"given":"Jingye","family":"Xu","sequence":"first","affiliation":[]},{"given":"Abinash","family":"Roy","sequence":"additional","affiliation":[]},{"given":"Masud H.","family":"Chowdhury","sequence":"additional","affiliation":[]}],"member":"98","reference":[{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.833615"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/82.673643"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.804706"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.856795"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.820651"},{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/92.894168"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.820651"},{"key":"21","volume-title":"Circuits, Interconnections and Packaging for VLSI","year":"1990"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/042829.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/042829.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,8]],"date-time":"2020-12-08T20:15:21Z","timestamp":1607458521000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2007\/042829\/abs\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,6,21]]},"references-count":8,"alternative-id":["042829","42829"],"URL":"https:\/\/doi.org\/10.1155\/2007\/42829","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"value":"1065-514X","type":"print"},{"value":"1563-5171","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007,6,21]]}}}