{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:24Z","timestamp":1740135924745,"version":"3.37.3"},"reference-count":13,"publisher":"Wiley","license":[{"start":{"date-parts":[[2007,4,30]],"date-time":"2007-04-30T00:00:00Z","timestamp":1177891200000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2007,4,30]]},"abstract":"<jats:p>High-performance long-range NoC link enables efficient implementation of network-on-chip topologies which inherently require high-performance long-distance point-to-point communication such as torus and fat-tree structures. In addition, the performance of other topologies, such as mesh, can be improved by using high-performance link between few selected remote nodes. We presented novel implementation of high-performance long-range NoC link based on multilevel current-mode signaling and delay-insensitive two-phase 1-of-4 encoding. Current-mode signaling reduces the communication latency of long wires significantly compared to voltage-mode signaling, making it possible to achieve high throughput without pipelining and\/or using repeaters. The performance of the proposed multilevel current-mode interconnect is analyzed and compared with two reference voltage mode interconnects. These two reference interconnects are designed using two-phase 1-of-4 encoded voltage-mode signaling, one with pipeline stages and the other using optimal repeater insertion. The proposed multilevel current-mode interconnect achieves higher throughput and lower latency than the two reference interconnects. Its throughput at 8 mm wire length is 1.222 GWord\/s which is 1.58 and 1.89 times higher than the pipelined and optimal repeater insertion interconnects, respectively. Furthermore, its power consumption is less than the optimal repeater insertion voltage-mode interconnect, at 10 mm wire length its power consumption is 0.75 mW while the reference repeater insertion interconnect is 1.066 mW. The effect of crosstalk is analyzed using four-bit parallel data transfer with the best-case and worst-case switching patterns and a transmission line model which has both capacitive coupling and inductive coupling.<\/jats:p>","DOI":"10.1155\/2007\/46514","type":"journal-article","created":{"date-parts":[[2007,5,10]],"date-time":"2007-05-10T08:22:07Z","timestamp":1178785327000},"page":"1-13","source":"Crossref","is-referenced-by-count":16,"title":["High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling"],"prefix":"10.1155","volume":"2007","author":[{"given":"Ethiopia","family":"Nigussie","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1995-343X","authenticated-orcid":true,"given":"Teijo","family":"Lehtonen","sequence":"additional","affiliation":[]},{"given":"Sampo","family":"Tuuna","sequence":"additional","affiliation":[]},{"given":"Juha","family":"Plosila","sequence":"additional","affiliation":[]},{"given":"Jouni","family":"Isoaho","sequence":"additional","affiliation":[]}],"member":"311","reference":[{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"volume-title":"Principles and Practices of Interconnection Networks","year":"2004","key":"2"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/43.828553"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1007\/BF01788562"},{"volume-title":"Digital Systems Engineering","year":"1998","key":"8"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.812366"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1049\/el:20064368"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/4.753686"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.808837"},{"key":"19","doi-asserted-by":"publisher","DOI":"10.1023\/B:ALOG.0000024066.66847.89"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.812509"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/92.805751"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/22.310584"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/046514.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/046514.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,8]],"date-time":"2020-12-08T20:17:15Z","timestamp":1607458635000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2007\/046514\/abs\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,4,30]]},"references-count":13,"alternative-id":["046514","46514"],"URL":"https:\/\/doi.org\/10.1155\/2007\/46514","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2007,4,30]]}}}