{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:07Z","timestamp":1740135907183,"version":"3.37.3"},"reference-count":7,"publisher":"Wiley","license":[{"start":{"date-parts":[[2007,10,29]],"date-time":"2007-10-29T00:00:00Z","timestamp":1193616000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2007,10,29]]},"abstract":"<jats:p>The severity of power consumption during parallel BIST of embedded memory\n\t cores is growing significantly. In order to alleviate this problem, a row bank-based precharge \n\t technique based on the divided wordline (DWL) architecture is proposed for low-power testing of embedded\n\t  SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row \n\t  bank-based precharge technique  is due to the predictable address sequence during test. In low-power test \n\t  mode, instead of precharging the entire memory array, only the current accessed row bank is\n\t   precharged. This will result in significant power saving for the precharge circuitry. The precharge power\n\t    can be reduced to <mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\"><mml:mrow><mml:mn>1<\/mml:mn><mml:mo>\/<\/mml:mo><mml:mi>b<\/mml:mi><\/mml:mrow><\/mml:math> of that of the traditional precharge techniques, where <mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\"><mml:mi>b<\/mml:mi><\/mml:math> denotes the number of row banks in the memory array. With simple transmission \ngates and inverters, the modified precharge control circuitry was also designed. The hardware \noverhead for implementing the low-power technique is almost negligible. Moreover, the corresponding\n BIST design to implement the low-power technique is almost the same as the conventional BIST \n designs. It is also notable that the inherent low-power characteristics of the DWL architecture can \n be preserved. According to experimental results, 48.9% power reduction can be achieved for \n a 256 <mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\"><mml:mo>\u00d7<\/mml:mo><\/mml:math> 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of \nrow banks increases, the power saving will also increase.<\/jats:p>","DOI":"10.1155\/2007\/67019","type":"journal-article","created":{"date-parts":[[2007,11,8]],"date-time":"2007-11-08T16:26:19Z","timestamp":1194539179000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Low-Power Built-In Self-Test Techniques for Embedded SRAMs"],"prefix":"10.1155","volume":"2007","author":[{"given":"Shyue-Kung","family":"Lu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6855-2360","authenticated-orcid":true,"given":"Yuang-Cheng","family":"Hsiao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chia-Hsiu","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun-Lin","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","reference":[{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1983.1051981"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826581"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/24.994929"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003802"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829797"},{"volume-title":"Testing Semiconductor Memories: Theory and Practice","year":"1998","key":"14"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-005-1169-1"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/067019.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/vlsi\/2007\/067019.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2007\/067019.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,8]],"date-time":"2020-12-08T20:29:18Z","timestamp":1607459358000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2007\/067019\/abs\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,10,29]]},"references-count":7,"alternative-id":["067019","67019"],"URL":"https:\/\/doi.org\/10.1155\/2007\/67019","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2007,10,29]]}}}