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The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry\u2010skip adders. The adder is implemented in 0.25\u2009<jats:italic>\u03bc<\/jats:italic>m CMOS technology at 3.3\u2009V. The critical delay for the proposed adder is 3.4\u2009nanoseconds. The simulation results show that the proposed adder is 18<jats:italic>%<\/jats:italic>faster than the current fastest carry\u2010skip adder.<\/jats:p>","DOI":"10.1155\/2008\/218565","type":"journal-article","created":{"date-parts":[[2008,4,3]],"date-time":"2008-04-03T17:05:45Z","timestamp":1207242345000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Delay Efficient 32\u2010Bit Carry\u2010Skip Adder"],"prefix":"10.1155","volume":"2008","author":[{"given":"Yu Shen","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Damu","family":"Radhakrishnan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2008,4,2]]},"reference":[{"key":"e_1_2_7_1_2","volume-title":"Computer Arithmetic Algorithms","author":"Koren I.","year":"2002"},{"key":"e_1_2_7_2_2","volume-title":"Computer Arithmetic Algorithms and Hardware Designs","author":"Parhami B.","year":"2000"},{"key":"e_1_2_7_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/82.539001"},{"key":"e_1_2_7_4_2","doi-asserted-by":"crossref","unstructured":"ChircaK. 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