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However these advantages come at the cost of a very high processing complexity and the efficient implementation of MIMO\u2010OFDM receivers is today a major research topic. In this paper, efficient architectures are proposed for the hardware implementation of the main building blocks of a MIMO\u2010OFDM receiver. A sphere decoder architecture flexible to different modulation without any loss in BER performance is presented while the proposed matrix factorization implementation allows to achieve the highest throughput specified in the IEEE 802.11n standard. Finally a novel<jats:italic>E<\/jats:italic><jats:sub>8<\/jats:sub>sphere decoder approach is presented, which allows for the realization of new golden space time trellis coded modulation (GST\u2010TCM) scheme. Implementation cost and offered throughput are provided for the proposed architectures synthesized on a 0.13\u2009<jats:italic>\u03bc<\/jats:italic><jats:italic>m<\/jats:italic>CMOS standard cell technology or on advanced FPGA devices.<\/jats:p>","DOI":"10.1155\/2008\/351962","type":"journal-article","created":{"date-parts":[[2008,3,30]],"date-time":"2008-03-30T08:19:25Z","timestamp":1206865165000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Enabling VLSI Processing Blocks for MIMO\u2010OFDM Communications"],"prefix":"10.1155","volume":"2008","author":[{"given":"Barbara","family":"Cerato","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guido","family":"Masera","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emanuele","family":"Viterbo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2008,3,24]]},"reference":[{"key":"e_1_2_6_1_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2005.844069"},{"key":"e_1_2_6_2_2","unstructured":"YaoH.andWornellG. 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Digital hardware aspects of multiantenna algorithms Ph.D. dissertation 2006 FebruaryDepartment of Electroscience Lund University Lund Sweden."}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2008\/351962.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2008\/351962.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2008\/351962","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,29]],"date-time":"2025-01-29T10:04:41Z","timestamp":1738145081000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2008\/351962"}},"subtitle":[],"editor":[{"given":"Jean-Baptiste","family":"Begueret","sequence":"additional","affiliation":[],"role":[{"role":"editor","vocabulary":"crossref"}]}],"short-title":[],"issued":{"date-parts":[[2008,1]]},"references-count":28,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2008,1]]}},"alternative-id":["10.1155\/2008\/351962"],"URL":"https:\/\/doi.org\/10.1155\/2008\/351962","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2008,1]]},"assertion":[{"value":"2007-04-30","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-01-17","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-03-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"351962"}}