{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T13:50:46Z","timestamp":1753883446899,"version":"3.41.2"},"reference-count":28,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2008,9,23]],"date-time":"2008-09-23T00:00:00Z","timestamp":1222128000000},"content-version":"vor","delay-in-days":266,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2008,1]]},"abstract":"<jats:p>In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells and allocated as \u201cwhitespace.\" This is done for a variety of reasons including the need for subsequent buffer insertion, as a means to ensure routability, signal integrity, and low coupling capacitance between wires, and to improve yield through DFM optimizations. To this end, layout constraints often require a certain minimum fraction of whitespace in each region of the chip. Our work introduces several techniques for allocation of whitespace in global, detail, and incremental placement. Our experiments show how to efficiently improve wirelength by reallocating whitespace in legal placements at the large scale. Additionally, for the first time in the literature, we empirically demonstrate high\u2010precision control of whitespace in designs with macros and obstacles. Our techniques consistently improve the quality of whitespace allocation of top\u2010down as well as analytical placement methods and achieve low penalties on designs from the ISPD 2006 placement contest with minimal interconnect increase.<\/jats:p>","DOI":"10.1155\/2008\/517919","type":"journal-article","created":{"date-parts":[[2008,9,25]],"date-time":"2008-09-25T13:04:33Z","timestamp":1222347873000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Fine Control of Local Whitespace in Placement"],"prefix":"10.1155","volume":"2008","author":[{"given":"Jarrod A.","family":"Roy","sequence":"first","affiliation":[]},{"given":"David A.","family":"Papa","sequence":"additional","affiliation":[]},{"given":"Igor L.","family":"Markov","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2008,9,23]]},"reference":[{"key":"e_1_2_8_1_2","doi-asserted-by":"crossref","unstructured":"AzzoniP. BertolettiM. DragoneN. FummiF. GuardianiC. andVendraminettoW. Yield-aware placement optimization Proceedings of Design Automation & Test in Europe (DATE \u203207) April 2007 Nice France 1232\u20131237 https:\/\/doi.org\/10.1109\/DATE.2007.364464.","DOI":"10.1109\/DATE.2007.364464"},{"key":"e_1_2_8_2_2","doi-asserted-by":"crossref","unstructured":"HuS.andhushiyan@ece.tamu.edu HuJ. jianghu@ece.tamu.edu Pattern sensitive placement for manufacturability Proceedings of International Symposium on Physical Design (ISPD \u203207) March 2007 Austin Tex USA 27\u201334 https:\/\/doi.org\/10.1145\/1231996.1232004.","DOI":"10.1145\/1231996.1232004"},{"key":"e_1_2_8_3_2","doi-asserted-by":"crossref","unstructured":"ChoM. mcho@ece.utexas.edu PanD. Z. dpan@ece.utexas.edu XiangH. andhuaxiang@us.ibm.com PuriR. ruchir@us.ibm.com Wire density driven global routing for CMP variation and timing Proceedings of International Conference on Computer-Aided Design (ICCAD \u203206) November 2006 San Jose Calif USA 487\u2013492 https:\/\/doi.org\/10.1109\/ICCAD.2006.320162.","DOI":"10.1145\/1233501.1233599"},{"key":"e_1_2_8_4_2","unstructured":"TSMC: Silicon Success http:\/\/www.tsmc.com\/download\/enliterature\/html-newsletter\/September03\/InDepth\/index.html."},{"key":"e_1_2_8_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.890096"},{"key":"e_1_2_8_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.818126"},{"key":"e_1_2_8_7_2","doi-asserted-by":"crossref","unstructured":"AdyaS. N. sadya@eecs.umich.edu MarkovI. L. andimarkov@eecs.umich.edu VillarrubiaP. G. pgvillar@us.ibm.com On whitespace and stability in mixed-size placement and physical synthesis Proceedings of International Conference on Computer-Aided Design (ICCAD \u203203) November 2003 San Jose Calif USA 311\u2013318 https:\/\/doi.org\/10.1109\/ICCAD.2003.1257687.","DOI":"10.1109\/ICCAD.2003.159705"},{"key":"e_1_2_8_8_2","doi-asserted-by":"crossref","first-page":"716","DOI":"10.1109\/TCAD.2003.818375","article-title":"Hierarchical whitespace allocation in top-down placement","volume":"22","author":"Caldwell A. E.","year":"2003","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_2_8_9_2","doi-asserted-by":"crossref","unstructured":"TangX. TianR. andWongM. D. R. Optimal redistribution of white space for wire length minimization 1 Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC \u203205) January 2005 Shanghai China 412\u2013417 https:\/\/doi.org\/10.1109\/ASPDAC.2005.1466198.","DOI":"10.1145\/1120725.1120900"},{"key":"e_1_2_8_10_2","doi-asserted-by":"crossref","unstructured":"CongJ. cong@cs.ucla.edu RomesisM. andmichalis@magma-da.com ShinnerlJ. R. shinnerl@cs.ucla.edu Robust mixed-size placement under tight white space constraints Proceedings of International Conference on Computer-Aided Design (ICCAD \u203205) November 2005 San Jose Calif USA 165\u2013172 https:\/\/doi.org\/10.1109\/ICCAD.2005.1560058.","DOI":"10.1109\/ICCAD.2005.1560058"},{"key":"e_1_2_8_11_2","doi-asserted-by":"crossref","unstructured":"SelvakkumaranN. selva@cs.umn.edu ParakhP. N. andparakh@mondes.com KarypisG. karypis@cs.umn.edu Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP \u203203) April 2003 Monterey Calif USA 53\u201359.","DOI":"10.1145\/639939.639941"},{"key":"e_1_2_8_12_2","doi-asserted-by":"crossref","unstructured":"NamG.-J. gnam@us.ibm.com ISPD 2006 placement contest: benchmark suite and results Proceedings of International Symposium on Physical Design (ISPD \u203206) April 2006 San Jose Calif USA.","DOI":"10.1145\/1123008.1123042"},{"key":"e_1_2_8_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907271"},{"key":"e_1_2_8_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.888260"},{"key":"e_1_2_8_15_2","doi-asserted-by":"crossref","unstructured":"NgA. N. aaronnn@umich.edu MarkovI. L. imarkov@umich.edu AggarwalR. andrajat.aggarwal@xilinx.com RamachandranV. venkyr@calypto.com Solving hard instances of floorplacement Proceedings of International Symposium on Physical Design (ISPD \u203206) April 2006 San Jose Calif USA 170\u2013177.","DOI":"10.1145\/1123008.1123047"},{"key":"e_1_2_8_16_2","doi-asserted-by":"crossref","unstructured":"YangX. ChoiB.-K. andSarrafzadehM. Routability driven white space allocation for fixed-die standard-cell placement Proceedings of International Symposium on Physical Design (ISPD \u203202) April 2002 Del Mar Calif USA 42\u201347.","DOI":"10.1145\/505397.505400"},{"key":"e_1_2_8_17_2","unstructured":"LiC. li35@ecn.purdue.edu XieM. xie@cs.ucla.edu KohC.-K. chengkok@ecn.purdue.edu CongJ. andcong@cs.ucla.edu MaddenP. H. pmadden@cs.binghamton.edu Routability-driven placement and white space allocation Proceedings of International Conference on Computer-Aided Design (ICCAD \u203204) November 2004 San Jose Calif USA 394\u2013401."},{"key":"e_1_2_8_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.892854"},{"key":"e_1_2_8_19_2","doi-asserted-by":"crossref","unstructured":"BrennerU.andVygenJ. Faster optimal single-row placement with fixed ordering Proceedings of Design Automation & Test in Europe (DATE \u203200) March 2000 Paris France 117\u2013121 https:\/\/doi.org\/10.1109\/DATE.2000.840026.","DOI":"10.1145\/343647.343716"},{"key":"e_1_2_8_20_2","doi-asserted-by":"crossref","unstructured":"RedaS.andsreda@cs.ucsd.edu ChowdharyA. amit.chowdhary@intel.com Effective linear programming based placement methods Proceedings of International Symposium on Physical Design (ISPD \u203206) April 2006 San Jose Calif USA 186\u2013191.","DOI":"10.1145\/1123008.1123049"},{"key":"e_1_2_8_21_2","doi-asserted-by":"publisher","DOI":"10.1006\/jagm.1995.0805"},{"key":"e_1_2_8_22_2","unstructured":"AlbrechtC. IWLS 2005 Benchmarks June 2005 http:\/\/iwls.org\/iwls2005\/benchmarks.html."},{"key":"e_1_2_8_23_2","doi-asserted-by":"crossref","unstructured":"ChanT. F. chan@math.ucla.edu CongJ. cong@cs.ucla.edu ShinnerlJ. R. shinnerl@cs.ucla.edu SzeK. andnksze@math.ucla.edu XieM. xie@cs.ucla.edu mPL6: enhanced multilevel mixed-size placement Proceedings of International Symposium on Physical Design (ISPD \u203206) April 2006 San Jose Calif USA 212\u2013214 https:\/\/doi.org\/10.1145\/1123008.1123055.","DOI":"10.1145\/1123008.1123055"},{"key":"e_1_2_8_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855969"},{"key":"e_1_2_8_25_2","doi-asserted-by":"crossref","unstructured":"CongJ.andcong@cs.ucla.edu LuoG. gluo@cs.ucla.edu Highly efficient gradient computation for density-constrained analytical placement methods Proceedings of International Symposium on Physical Design (ISPD \u203208) April 2008 Portland Ore USA 39\u201346 https:\/\/doi.org\/10.1145\/1353629.1353639.","DOI":"10.1145\/1353629.1353639"},{"key":"e_1_2_8_26_2","doi-asserted-by":"crossref","unstructured":"CongJ.andcong@cs.ucla.edu XieM. xie@cs.ucla.edu A robust detailed placement for mixed-size IC designs Proceedings 11th Asia and South Pacific Design Automation Conference (ASP-DAC \u203206) January 2006 Yokohama Japan 188\u2013194.","DOI":"10.1145\/1118299.1118353"},{"key":"e_1_2_8_27_2","doi-asserted-by":"crossref","unstructured":"AdyaS. N. saurabh@synplicity.com ChaturvediS. shubhyant.chaturvedi@amd.com RoyJ. A. royj@umich.edu PapaD. A. andiamyou@umich.edu MarkovI. L. imarkov@umich.edu Unification of partitioning placement and floorplanning Proceedings of International Conference on Computer-Aided Design (ICCAD \u203204) November 2004 San Jose Calif USA 550\u2013557.","DOI":"10.1109\/ICCAD.2004.1382639"},{"key":"e_1_2_8_28_2","doi-asserted-by":"crossref","unstructured":"ChenT.-C. donnie@eda.ee.ntu.edu.tw ChoM. thyeros@cerc.utexas.edu PanD. Z. anddpan@ece.utexas.edu ChangY.-W. ywchang@cc.ee.ntu.edu.tw Metal-density driven placement for CMP variation and routability Proceedings of International Symposium on Physical Design (ISPD \u203208) April 2008 Portland Ore USA 31\u201338 https:\/\/doi.org\/10.1145\/1353629.1353638.","DOI":"10.1145\/1353629.1353638"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2008\/517919.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2008\/517919.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2008\/517919","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T02:35:54Z","timestamp":1738377354000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2008\/517919"}},"subtitle":[],"editor":[{"given":"Spyros","family":"Tragoudas","sequence":"additional","affiliation":[]}],"short-title":[],"issued":{"date-parts":[[2008,1]]},"references-count":28,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2008,1]]}},"alternative-id":["10.1155\/2008\/517919"],"URL":"https:\/\/doi.org\/10.1155\/2008\/517919","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2008,1]]},"assertion":[{"value":"2007-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-08-04","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2008-09-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"517919"}}