{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,4,19]],"date-time":"2024-04-19T06:28:51Z","timestamp":1713508131998},"reference-count":3,"publisher":"Hindawi Limited","license":[{"start":{"date-parts":[[2008,1,1]],"date-time":"2008-01-01T00:00:00Z","timestamp":1199145600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["International Journal of Reconfigurable Computing"],"published-print":{"date-parts":[[2008]]},"abstract":"<jats:p>This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining\u2014where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read\/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.<\/jats:p>","DOI":"10.1155\/2008\/674340","type":"journal-article","created":{"date-parts":[[2008,11,27]],"date-time":"2008-11-27T09:13:17Z","timestamp":1227777197000},"page":"1-14","source":"Crossref","is-referenced-by-count":1,"title":["Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation"],"prefix":"10.1155","volume":"2008","author":[{"given":"Johan","family":"Ditmar","sequence":"first","affiliation":[{"name":"Kellogg College, University of Oxford, 62 Banbury Road, Oxford OX2 6PN, UK"}]},{"given":"Steve","family":"McKeever","sequence":"additional","affiliation":[{"name":"Oxford University Computing Laboratory, Wolfson Building, Parks Road, Oxford OX1 3QD, UK"}]},{"given":"Alex","family":"Wilson","sequence":"additional","affiliation":[{"name":"Celoxica Ltd., 66 Milton Park, Abingdon, Oxfordshire OX14 4RX, UK"}]}],"member":"98","reference":[{"key":"4","year":"1994"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1027084.1027087"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1986.1270207"}],"container-title":["International Journal of Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2008\/674340.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2008\/674340.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2008\/674340.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,8,11]],"date-time":"2016-08-11T15:46:44Z","timestamp":1470930404000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.hindawi.com\/journals\/ijrc\/2008\/674340\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008]]},"references-count":3,"alternative-id":["674340","674340"],"URL":"https:\/\/doi.org\/10.1155\/2008\/674340","relation":{},"ISSN":["1687-7195","1687-7209"],"issn-type":[{"value":"1687-7195","type":"print"},{"value":"1687-7209","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008]]}}}