{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T14:57:41Z","timestamp":1740149861628,"version":"3.37.3"},"reference-count":4,"publisher":"Wiley","license":[{"start":{"date-parts":[[2008,1,1]],"date-time":"2008-01-01T00:00:00Z","timestamp":1199145600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/D060567\/1","EP\/C549481\/1"],"award-info":[{"award-number":["EP\/D060567\/1","EP\/C549481\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/D060567\/1","EP\/C549481\/1"],"award-info":[{"award-number":["EP\/D060567\/1","EP\/C549481\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["International Journal of Reconfigurable Computing"],"published-print":{"date-parts":[[2008]]},"abstract":"<jats:p>This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I\/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I\/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used.<\/jats:p>","DOI":"10.1155\/2008\/736203","type":"journal-article","created":{"date-parts":[[2009,2,25]],"date-time":"2009-02-25T10:06:12Z","timestamp":1235556372000},"page":"1-10","source":"Crossref","is-referenced-by-count":0,"title":["The Coarse-Grained\/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units"],"prefix":"10.1155","volume":"2008","author":[{"given":"Chi Wai","family":"Yu","sequence":"first","affiliation":[{"name":"Department of Computing, Imperial College London, London SW7 2AZ, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Julien","family":"Lamoureux","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, British Columbia, Canada V6T 1Z4"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J. E.","family":"Wilton","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, British Columbia, Canada V6T 1Z4"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philip H. 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