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Pixel subsampling \n      is performed in the selected candidate blocks which significantly reduces computational\n       cost with low quality degradation. The architecture developed is a fully pipelined\n        parallel design with 9 processing elements. Two different methods are \n       deployed to reduce the power consumption, parallel and pipelined implementation and \n       parallel accessing to memory. For processing 30 CIF frames per second our\n        architecture requires a clock frequency of 4.5\u2009MHz.<\/jats:p>","DOI":"10.1155\/2008\/890410","type":"journal-article","created":{"date-parts":[[2008,4,24]],"date-time":"2008-04-24T15:37:19Z","timestamp":1209051439000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Fully Pipelined Parallel Architecture for Candidate Block and Pixel\u2010Subsampling\u2010Based Motion Estimation"],"prefix":"10.1155","volume":"2008","author":[{"given":"Reeba","family":"Korah","sequence":"first","affiliation":[]},{"given":"J.Raja Paul","family":"Perinbam","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2008,4,20]]},"reference":[{"key":"e_1_2_8_1_2","doi-asserted-by":"crossref","unstructured":"ArtieriA.andJutandF. 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