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The 16\u2010bit 1024\u2010point FFT with the R2<jats:sup>2<\/jats:sup>SDF architecture had a maximum clock frequency of 95.2 MHz and used 2802 slices on the Spartan\u20103, a throughput per area ratio of 0.034 Msamples\/s\/slice. The R4SDC architecture ran at 123.8\u2009MHz and used 4409 slices on the Spartan\u20103, a throughput per area ratio of 0.028 Msamples\/s\/slice. On Virtex\u20104, the 16\u2010bit 1024\u2010point R2<jats:sup>2<\/jats:sup>SDF architecture ran at 235.6 MHz and used 2256 slice, giving a 0.104 Msamples\/s\/slice ratio; the 16\u2010bit 1024\u2010point R4SDC architecture ran at 219.2\u2009MHz and used 3064 slices, giving a 0.072 Msamples\/s\/slice ratio. The R2<jats:sup>2<\/jats:sup>SDF was more efficient than the R4SDC in terms of throughput per area due to a simpler controller and an easier balanced rounding scheme. This paper also shows that balanced stage rounding is an appropriate rounding scheme for pipeline FFT processors.<\/jats:p>","DOI":"10.1155\/2009\/219140","type":"journal-article","created":{"date-parts":[[2009,9,14]],"date-time":"2009-09-14T14:01:06Z","timestamp":1252936866000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":44,"title":["Pipeline FFT Architectures Optimized for FPGAs"],"prefix":"10.1155","volume":"2009","author":[{"given":"Bin","family":"Zhou","sequence":"first","affiliation":[]},{"given":"Yingning","family":"Peng","sequence":"additional","affiliation":[]},{"given":"David","family":"Hwang","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2009,9,14]]},"reference":[{"key":"e_1_2_7_1_2","volume-title":"Theory and Application of Digital Signal Processing","author":"Rabiner L. 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