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The effect of variation in LUT and cluster size on the area, performance, and power of the Tree\u2010based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR\u2010style Mesh.<\/jats:p>","DOI":"10.1155\/2009\/259837","type":"journal-article","created":{"date-parts":[[2009,10,13]],"date-time":"2009-10-13T14:50:27Z","timestamp":1255445427000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":47,"title":["FPGA Interconnect Topologies Exploration"],"prefix":"10.1155","volume":"2009","author":[{"given":"Zied","family":"Marrakchi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hayder","family":"Mrabet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Umer","family":"Farooq","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2009,10,13]]},"reference":[{"key":"e_1_2_7_1_2","doi-asserted-by":"crossref","unstructured":"DeHonA. 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