{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:36:44Z","timestamp":1753886204303,"version":"3.41.2"},"reference-count":32,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2009,9,14]],"date-time":"2009-09-14T00:00:00Z","timestamp":1252886400000},"content-version":"vor","delay-in-days":256,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["International Journal of Reconfigurable Computing"],"published-print":{"date-parts":[[2009,1]]},"abstract":"<jats:p>A reconfigurable systolic array (RSA) architecture that supports the realization of DSP functions for multicarrier wireless and\nmultirate applications is presented. The RSA consists of coarse\u2010grained processing elements that can be configured as complex\nDSP functions that are the basic building blocks of Polyphase\u2010FIR filters, phase shifters, DFTs, and Polyphase\u2010DFT circuits. The\nhomogeneous characteristic of the RSA architecture, where each reconfigurable processing element (PE) cell is connected to its\nnearest neighbors via configurable switch (SW) elements, enables array expansion for parallel processing and facilitates time\nsharing computation of high\u2010throughput data by individual PEs. For DFT circuit configurations, an algorithmic optimization\ntechnique has been employed to reduce the overall number of vector\u2010matrix products to be mapped on the RSA. The hardware\ncomplexity and throughput of the RSA\u2010based DFT structures have been evaluated and compared against several conventional\nmodular FFT realizations. Designs and circuit implementations of the PE cell and several RSAs configured as DFT and Polyphase\nfilter circuits are also presented. The RSA architecture offers significant flexibility and computational\ncapacity for applications that require real time reconfiguration and high\u2010density computing.<\/jats:p>","DOI":"10.1155\/2009\/529512","type":"journal-article","created":{"date-parts":[[2009,9,14]],"date-time":"2009-09-14T14:01:06Z","timestamp":1252936866000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications"],"prefix":"10.1155","volume":"2009","author":[{"given":"H.","family":"Ho","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.","family":"Szwarc","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Kwasniewski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2009,9,14]]},"reference":[{"key":"e_1_2_9_1_2","unstructured":"ETSI Digital Video Broadcasting (DVB); Framing Structure Channel Coding and Modulation for Digital Terrestrial Television EN 300 744 v1.5.1 2004."},{"key":"e_1_2_9_2_2","unstructured":"ETSI Radio Broadcasting Systems; Digital Audio Broadcasting (DAB) to Mobile Portable and Fixed Receivers EN 300 401 v1.4.1 2006."},{"key":"e_1_2_9_3_2","unstructured":"IEEE STD 802.11a High-Speed Physical Layer in 5 GHz Band 1999 http:\/\/ieee802.org."},{"key":"e_1_2_9_4_2","unstructured":"WPAN Working Group http:\/\/grouper.ieee.org\/groups\/802\/15."},{"key":"e_1_2_9_5_2","unstructured":"ETSI Broadband Radio Access Networks (BRAN); HIPERLAN Type 2 Physical (PHY) layer TS 101 475 v1.1.1 April 2000."},{"key":"e_1_2_9_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/11.992857"},{"key":"e_1_2_9_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/5.52200"},{"volume-title":"Multirate Digital Signal Processing","year":"1994","author":"Fliege N. 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