{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:40:01Z","timestamp":1753886401263,"version":"3.41.2"},"reference-count":31,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2009,12,8]],"date-time":"2009-12-08T00:00:00Z","timestamp":1260230400000},"content-version":"vor","delay-in-days":341,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"name":"Spanish Ministry of Education and Science","award":["TEC2006-13067-C03-03"],"award-info":[{"award-number":["TEC2006-13067-C03-03"]}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["International Journal of Reconfigurable Computing"],"published-print":{"date-parts":[[2009,1]]},"abstract":"<jats:p>We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed\u2010point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength\u2010wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA\u2010wise resource usage metric that enables an efficient distribution of logic fabric and embedded DSP resources. The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed\u2010point datapaths and (ii) the benefits of a wise use of embedded FPGA resources. The use of a complete fixed\u2010point datapath leads to improvements up to 35%. And, the wise mapping of operations to FPGA resources (logic fabric and embedded blocks), thanks to the proposed resource usage metric, leads to improvements up to 54%.<\/jats:p>","DOI":"10.1155\/2009\/703267","type":"journal-article","created":{"date-parts":[[2009,12,9]],"date-time":"2009-12-09T12:51:22Z","timestamp":1260363082000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["Architectural Synthesis of Fixed\u2010Point DSP Datapaths Using FPGAs"],"prefix":"10.1155","volume":"2009","author":[{"given":"Gabriel","family":"Caffarena","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juan A.","family":"L\u00f3pez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gerardo","family":"Leyva","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carlos","family":"Carreras","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Octavio","family":"Nieto-Taladriz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2009,12,8]]},"reference":[{"key":"e_1_2_6_1_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.936374"},{"key":"e_1_2_6_2_2","doi-asserted-by":"crossref","unstructured":"ConstantinidesG. CheungP. andLukW. Heuristic datapath allocation for multiple wordlength systems Proceedings of the Conference on Design Automation and Test in Europe (DATE \u203201) 2001 Munich Germany 791\u2013796.","DOI":"10.1109\/DATE.2001.915122"},{"key":"e_1_2_6_3_2","doi-asserted-by":"crossref","unstructured":"CongJ. FanY. HanG.et al. Bitwidth-aware scheduling and binding in high-level synthesis Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC \u203205) 2005 Shanghai China 856\u2013861.","DOI":"10.1145\/1120725.1121055"},{"key":"e_1_2_6_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.862175"},{"key":"e_1_2_6_5_2","doi-asserted-by":"crossref","unstructured":"WadekarS. A.andParkerA. C. Accuracy sensitive word-length selection for algorithm optimization Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD \u203298) 1998 San Jose Calif USA 54\u201361 2-s2.0-0032302589.","DOI":"10.1109\/ICCD.1998.727023"},{"key":"e_1_2_6_6_2","doi-asserted-by":"crossref","unstructured":"CaffarenaG. L\u00f3pezJ. A. CarrerasC. andNieto-TaladrizO. High-level synthesis of multiple word-length DSP algorithms using heterogeneous-resource FPGAS Proceedings of the International Conference on Field Programmable Logic and Applications (FPL \u203206) 2006 Madrid Spain 675\u2013678 2-s2.0-0031147547 https:\/\/doi.org\/10.1109\/FPL.2006.311288.","DOI":"10.1109\/FPL.2006.311288"},{"key":"e_1_2_6_7_2","doi-asserted-by":"crossref","unstructured":"NayakA. HaldarM. ChoudharyA. andBanerjeeP. Accurate area and delay estimators for FPGAs Proceedings of the 39th Design Automation Conference (DAC \u203202) June 2002 New Orleans La USA 862\u2013869.","DOI":"10.1109\/DATE.2002.998400"},{"key":"e_1_2_6_8_2","doi-asserted-by":"crossref","unstructured":"BouganisC.-S. ConstantinidesG. A. andCheungP. Y. K. A novel 2D filter design methodology for heterogeneous devices Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM \u203205) April 2005 Napa Calif USA 13\u201322 https:\/\/doi.org\/10.1109\/FCCM.2005.10 2-s2.0-33746160312.","DOI":"10.1109\/FCCM.2005.10"},{"key":"e_1_2_6_9_2","unstructured":"LiangX. VetterJ. S. SmithM. C. andBlandA. S. Balancing FPGA resource utilities Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA \u203205) June 2005 Las Vegas Nev USA 156\u2013162 2-s2.0-18644369928."},{"key":"e_1_2_6_10_2","doi-asserted-by":"crossref","unstructured":"SmithA. M. ConstantinidesG. A. andCheungP. Y. K. Fused-arithmetic unit generation for reconfigurable devices using common subgraph extraction Proceedings of the International Conference on Field Programmable Technology (FPT \u203207) December 2007 Kitakyushu Japan 105\u2013112 2-s2.0-34147186108 https:\/\/doi.org\/10.1109\/FPT.2007.4439238.","DOI":"10.1109\/FPT.2007.4439238"},{"key":"e_1_2_6_11_2","doi-asserted-by":"publisher","DOI":"10.1155\/ES\/2006\/23197"},{"key":"e_1_2_6_12_2","doi-asserted-by":"crossref","unstructured":"Herv\u00e9N. M\u00e9nardD. andSentieysO. About the importance of operation grouping procedures for multiple word-length architecture optimizations Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC \u203207) March 2007 191\u2013200 2-s2.0-33846965181.","DOI":"10.1007\/978-3-540-71431-6_18"},{"key":"e_1_2_6_13_2","series-title":"Electrical and Computer Engineering series","volume-title":"Synthesis and Optimization of Digital Circuits","author":"De Michelli G.","year":"1994"},{"key":"e_1_2_6_14_2","doi-asserted-by":"crossref","unstructured":"CantinM.-A. SavariaY. ProdanosD. andLavoieP. An automatic word length determination method 5 Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS \u203201) May 2001 Sydney Australia 53\u201356 2-s2.0-0034999506.","DOI":"10.1109\/ISCAS.2001.921982"},{"key":"e_1_2_6_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.818119"},{"key":"e_1_2_6_16_2","doi-asserted-by":"publisher","DOI":"10.1155\/ES\/2006\/64913"},{"key":"e_1_2_6_17_2","doi-asserted-by":"crossref","unstructured":"CaffarenaG. L\u00f3pezJ. A. CarrerasC. andNieto-TaladrizO. Optimized implementation of DSP cores on FPGAs using logic-based and embedded resources Proceedings of the International Symposium on System-On-Chip (SoC \u203206) November 2006 Tampere Finland 103\u2013106.","DOI":"10.1109\/ISSOC.2006.321978"},{"key":"e_1_2_6_18_2","doi-asserted-by":"crossref","unstructured":"EnzlerR. JegerT. CottetD. andTr\u00f6sterG. High-level area and performance estimation of hardware building blocks on FPGAs Proceedings of the International Conference on Field Programmable Logic and Applications (FBL \u203200) August 2000 Villach Austria 525\u2013534.","DOI":"10.1007\/3-540-44614-1_57"},{"key":"e_1_2_6_19_2","doi-asserted-by":"crossref","unstructured":"SchoofsK. GoossensG. andDe ManH. Bit-alignment in hardware allocation for multiplexed DSP architectures Proceedings of the Conference on Design Automation and Test in Europe (DATE \u203293) October 1993 289\u2013293.","DOI":"10.1109\/EDAC.1993.386461"},{"key":"e_1_2_6_20_2","doi-asserted-by":"publisher","DOI":"10.1126\/science.220.4598.671"},{"key":"e_1_2_6_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/78.124942"},{"key":"e_1_2_6_22_2","doi-asserted-by":"crossref","unstructured":"OrsilaH. KangasT. SalminenE. andH\u00e4m\u00e4l\u00e4inenT. D. Parameterizing simulated annealing for distributing task graphs on multiprocessor SoCs Proceedings of the International Symposium on System-On-Chip (SoC \u203206) November 2006 Tampere Finland 1\u20134 https:\/\/doi.org\/10.1109\/ISSOC.2006.321971 2-s2.0-50049087101.","DOI":"10.1109\/ISSOC.2006.321971"},{"key":"e_1_2_6_23_2","doi-asserted-by":"crossref","unstructured":"Lopez-VallejoM. GrajalJ. andLopezJ. Constraintdriven system partitioning Proceedings of the Conference on Design Automation and Test in Europe (DATE \u203200) March 2000 Paris France 411\u2013416.","DOI":"10.1109\/DATE.2000.840304"},{"key":"e_1_2_6_24_2","doi-asserted-by":"crossref","first-page":"458","DOI":"10.1109\/43.631209","article-title":"A unified lower bound estimation technique for high-level synthesis","volume":"16","author":"Ohm S. Y.","year":"1997","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_2_6_25_2","doi-asserted-by":"crossref","unstructured":"CaffarenaG. L\u00f3pezJ. A. LeyvaG. CarrerasC. andNieto-TaladrizO. Optmized architectural synthesis of fixed-point datapaths Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig \u203208) 2008 Cancun Mexico 85\u201390.","DOI":"10.1109\/ReConFig.2008.48"},{"key":"e_1_2_6_26_2","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1145\/785411.785412","article-title":"On the hardware-software partitioning problem: System modeling and partitioning techniques","volume":"8","author":"L\u00f3pez-Vallejo M.","year":"2003","journal-title":"ACM Transactions on Design Automation of Electronic Systems (TODAES)"},{"key":"e_1_2_6_27_2","doi-asserted-by":"publisher","DOI":"10.1049\/iet\u2010cds:20070198"},{"key":"e_1_2_6_28_2","doi-asserted-by":"crossref","unstructured":"CantinM.-A. SavariaY. andLavoieP. A comparison of automatic word length optimization procedures 2 Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS \u203202) May 2002 612\u2013615 2-s2.0-0036286912.","DOI":"10.1109\/ISCAS.2002.1011427"},{"volume-title":"VLSI Digital Signal Processing Systems: Design and Implementation","year":"1999","author":"Parhi K. K.","key":"e_1_2_6_29_2"},{"key":"e_1_2_6_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/82.868453"},{"key":"e_1_2_6_31_2","unstructured":"CaffarenaG. Combined word-length allocation and high-level synthesis of digital signal processing circuits Ph.D. dissertation 2008 Universidad Polit\u00e9cnica de Madrid Madrid Spain."}],"container-title":["International Journal of Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2009\/703267.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2009\/703267.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2009\/703267","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,13]],"date-time":"2025-02-13T19:00:00Z","timestamp":1739473200000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2009\/703267"}},"subtitle":[],"editor":[{"given":"Cesar","family":"Torres","sequence":"additional","affiliation":[],"role":[{"role":"editor","vocabulary":"crossref"}]}],"short-title":[],"issued":{"date-parts":[[2009,1]]},"references-count":31,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2009,1]]}},"alternative-id":["10.1155\/2009\/703267"],"URL":"https:\/\/doi.org\/10.1155\/2009\/703267","archive":["Portico"],"relation":{},"ISSN":["1687-7195","1687-7209"],"issn-type":[{"type":"print","value":"1687-7195"},{"type":"electronic","value":"1687-7209"}],"subject":[],"published":{"date-parts":[[2009,1]]},"assertion":[{"value":"2009-02-25","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-08-28","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2009-12-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"703267"}}