{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T13:52:52Z","timestamp":1753883572332,"version":"3.41.2"},"reference-count":18,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2009,7,15]],"date-time":"2009-07-15T00:00:00Z","timestamp":1247616000000},"content-version":"vor","delay-in-days":195,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["Ma 1412\/5"],"award-info":[{"award-number":["Ma 1412\/5"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["International Journal of Reconfigurable Computing"],"published-print":{"date-parts":[[2009,1]]},"abstract":"<jats:p>Runtime reconfigurable system\u2010on\u2010chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a\nchanging number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement\nof processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually\ninstantiated processing modules. While few works address the design of flexible system architectures, the adjustment of\nboundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered\ndue to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows\nfor a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. \nThis technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex\u20104\nFPGAs. The system architecture will also be presented to provide a realistic application example.<\/jats:p>","DOI":"10.1155\/2009\/942930","type":"journal-article","created":{"date-parts":[[2009,7,15]],"date-time":"2009-07-15T14:59:48Z","timestamp":1247669988000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime"],"prefix":"10.1155","volume":"2009","author":[{"given":"Thilo","family":"Pionteck","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roman","family":"Koch","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carsten","family":"Albrecht","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Erik","family":"Maehle","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2009,7,15]]},"reference":[{"key":"e_1_2_8_1_2","doi-asserted-by":"crossref","unstructured":"LysaghtP. patrick.lysaght@xilinx.com BlodgetB. brandon.blodget@xilinx.com MasonJ. jeff.mason@xilinx.com YoungJ. andjay.young@xilinx.com BridgfordB. brendan.bridgford@xilinx.com Invited paper: enhanced architectures design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAS Proceedings of the International Conference on Field Programmable Logic and Applications (FPL \u203206) August 2006 Madrid Spain 12\u201317 EID2-s2.0-1642346948 https:\/\/doi.org\/10.1109\/FPL.2006.311188.","DOI":"10.1109\/FPL.2006.311188"},{"key":"e_1_2_8_2_2","unstructured":"PlanAhead the Fastest Route to Better Design Data sheet 2005."},{"key":"e_1_2_8_3_2","doi-asserted-by":"publisher","DOI":"10.1142\/S0129626408003387"},{"key":"e_1_2_8_4_2","unstructured":"DittmannF. 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Algorithmic skeletons for the programming of reconfigurable systems 4761 Proceedings of the 5th IFIP International Workshop on Software Technologies for Embedded and Ubiquitous Systems (SEUS \u203207) May 2007 Santorini Island Greece Springer 358\u2013367 Lecture Notes in Computer Science EID2-s2.0-1842852979."},{"key":"e_1_2_8_5_2","doi-asserted-by":"crossref","unstructured":"DittmannF. roichen@upb.de FrankS. andsfrank@upb.de Oberth\u00fcrS. oberthuer@upb.de Algorithmic skeletons for the design of partially reconfigurable systems Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium (IPDPS \u203208) April 2008 Miami Fla USA 1\u20138 EID2-s2.0-1842852979 https:\/\/doi.org\/10.1109\/IPDPS.2008.4536509.","DOI":"10.1109\/IPDPS.2008.4536509"},{"volume-title":"Structured Management of Parallel Computing","year":"1989","author":"Cole M.","key":"e_1_2_8_6_2"},{"key":"e_1_2_8_7_2","doi-asserted-by":"crossref","unstructured":"H\u00fcbnerM. huebner@itiv.uni-karlsruhe.de SchuckC. andschuck@itiv.uni-karlsruhe.de BeckerJ. becker@itiv.uni-karlsruhe.de Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs Proceedings of the 13th Workshop on Reconfigurable Architectures (RAW \u203206) April 2006 Rhodes Greece 1\u20138 EID2-s2.0-33847121786 https:\/\/doi.org\/10.1109\/IPDPS.2006.1639449.","DOI":"10.1109\/IPDPS.2006.1639449"},{"key":"e_1_2_8_8_2","doi-asserted-by":"crossref","unstructured":"SchuckC. schuck@itiv.uni-karlsruhe.de K\u00fchnleM. kuehnle@itiv.uni-karlsruhe.de H\u00fcbnerM. andhuebner@itiv.uni-karlsruhe.de BeckerJ. becker@itiv.uni-karlsruhe.de A framework for dynamic 2D placement on FPGAs Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium (IPDPS \u203208) April 2008 Miami Fla USA 1\u20137 EID2-s2.0-0141928907 https:\/\/doi.org\/10.1109\/IPDPS.2008.4536512.","DOI":"10.1109\/IPDPS.2008.4536512"},{"key":"e_1_2_8_9_2","unstructured":"GuccioneS. LeviD. andSundararajanP. Bits: Java based interface for reconfigurable computing Proceedings of the 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies (MAPLD \u203299) 1999."},{"key":"e_1_2_8_10_2","doi-asserted-by":"crossref","unstructured":"HagemeyerJ. jenze@hni.uni-paderborn.de KettelhoitB. boris@hni.uni-paderborn.de KoesterM. andkoester@hni.uni-paderborn.de PorrmannM. porrmann@hni.uni-paderborn.de A design methodology for communication infrastructures on partially reconfigurable FPGAs Proceedings of the International Conference on Field Programmable Logic and Applications (FPL \u203207) August 2007 Amsterdam The Netherlands 331\u2013338 EID2-s2.0-8744312724 https:\/\/doi.org\/10.1109\/FPL.2007.4380668.","DOI":"10.1109\/FPL.2007.4380668"},{"key":"e_1_2_8_11_2","doi-asserted-by":"crossref","unstructured":"KohS.andDiesselO. COMMA: a communications methodology for dynamic module reconfiguration in FPGAs Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM \u203206) April 2006 Napa Calif USA 273\u2013274 EID2-s2.0-34547401647 https:\/\/doi.org\/10.1109\/FCCM.2006.32.","DOI":"10.1109\/FCCM.2006.32"},{"key":"e_1_2_8_12_2","doi-asserted-by":"crossref","unstructured":"KohS.andshannonk@cse.unsw.edu.au DiesselO. odiessel@cse.unsw.edu.au Communications infrastructure generation for modular FPGA reconfiguration Proceedings of the IEEE International Conference on Field Programmable Technology (FPT \u203206) December 2006 Bangkok Thailand 321\u2013324 EID2-s2.0-43749101520 https:\/\/doi.org\/10.1109\/FPT.2006.270338.","DOI":"10.1109\/FPT.2006.270338"},{"key":"e_1_2_8_13_2","doi-asserted-by":"crossref","unstructured":"HortaE. L. LockwoodJ. W. TaylorD. andParlourD. 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