{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:43:51Z","timestamp":1753886631200,"version":"3.41.2"},"reference-count":8,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2010,6,28]],"date-time":"2010-06-28T00:00:00Z","timestamp":1277683200000},"content-version":"vor","delay-in-days":178,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Journal of Electrical and Computer Engineering"],"published-print":{"date-parts":[[2010,1]]},"abstract":"<jats:p>Switching Architectures deploying shareable parallel memory modules are quite versatile in their ability to scale to higher capacity while retaining the advantage of sharing its entire memory resource among all input and output ports. The two main classes of such architectures, namely, the Shared Multibuffer\u2010(SMB\u2010) based switch and the Sliding\u2010Window\u2010(SW\u2010) based packet switch, both deploy parallel memory modules that are physically separate but logically connected. Inspite of their similarity in regards to using shareable parallel memory modules, they differ in switching control and scheduling of packets to parallel memory modules. SMB switch uses centralized control whereas the SW switch uses a decentralized control for switching operations. In this paper, we present a new memory assignment scheme for the Sliding\u2010Window (SW) switch for assigning packets to parallel memory modules that maximizes the parallel storage of packets to multiple memory modules. We compare the performance of a sliding\u2010window switch deploying this new memory assignment scheme with that of an SMB switch architecture under conditions of identical traffic type and memory resources deployed. The simulation results show that the new memory assignment scheme for the sliding window switch maximizes parallel storage of packets input in a given switch cycle, and it does not require speed\u2010up of memory modules. Furthermore, it provides a superior performance compared to that of the SMB switch under the constraints of fixed memory\u2010bandwidth and memory resources.<\/jats:p>","DOI":"10.1155\/2010\/126591","type":"journal-article","created":{"date-parts":[[2010,6,28]],"date-time":"2010-06-28T14:35:58Z","timestamp":1277735758000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Comparison of Memory Assignment Schemes for Switch Architectures with Shareable Parallel Memory Modules"],"prefix":"10.1155","volume":"2010","author":[{"given":"Sanjeev","family":"Kumar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alvaro","family":"Munoz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2010,6,28]]},"reference":[{"key":"e_1_2_7_1_2","doi-asserted-by":"publisher","DOI":"10.1002\/0471224405"},{"key":"e_1_2_7_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCOM.1978.1094076"},{"key":"e_1_2_7_3_2","unstructured":"OshimaK. YamanakaH. SaitoH.et al. A new ATM switch architecture based on STS-type shared buffering and its implementation 1 Proceedings of the 14th International Switching Symposium (ISS \u203292) October 1992 359\u2013363."},{"key":"e_1_2_7_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/49.594840"},{"key":"e_1_2_7_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2003.810513"},{"key":"e_1_2_7_6_2","doi-asserted-by":"crossref","unstructured":"MunozA.andCantrellC. D. Memory-configuration and memory-bandwidth in the Sliding-Window (SW) switch architecture Proceedings of the 52nd Midwest Symposium on Circuits and Systems (MWSCAS \u203209) August 2009 288\u2013291 2-s2.0-25444475840 https:\/\/doi.org\/10.1109\/MWSCAS.2009.5236097.","DOI":"10.1109\/MWSCAS.2009.5236097"},{"key":"e_1_2_7_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/LCOMM.2005.11021"},{"key":"e_1_2_7_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/90.664262"}],"container-title":["Journal of Electrical and Computer Engineering"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2010\/126591.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2010\/126591.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2010\/126591","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,19]],"date-time":"2024-06-19T10:28:40Z","timestamp":1718792920000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2010\/126591"}},"subtitle":[],"editor":[{"given":"Edward","family":"Au","sequence":"additional","affiliation":[],"role":[{"role":"editor","vocabulary":"crossref"}]}],"short-title":[],"issued":{"date-parts":[[2010,1]]},"references-count":8,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2010,1]]}},"alternative-id":["10.1155\/2010\/126591"],"URL":"https:\/\/doi.org\/10.1155\/2010\/126591","archive":["Portico"],"relation":{},"ISSN":["2090-0147","2090-0155"],"issn-type":[{"type":"print","value":"2090-0147"},{"type":"electronic","value":"2090-0155"}],"subject":[],"published":{"date-parts":[[2010,1]]},"assertion":[{"value":"2009-10-31","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-04-21","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2010-06-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"126591"}}