{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T14:47:10Z","timestamp":1742395630224,"version":"3.37.3"},"reference-count":9,"publisher":"Wiley","license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100004809","name":"Financiadora de Estudos e Projetos","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["International Journal of Reconfigurable Computing"],"published-print":{"date-parts":[[2011]]},"abstract":"<jats:p>This paper describes a comparison of two Montgomery modular multiplication architectures: a systolic and a multiplexed. Both implementations target FPGA devices. The modular multiplication is employed in modular exponentiation processes, which are the most important operations of some public-key cryptographic algorithms, including the most popular of them, the RSA. The proposed systolic architecture presents a high-radix implementation with a one-dimensional array of Processing Elements. The multiplexed implementation is a new alternative and is composed of multiplier blocks in parallel with the new simplified Processing Elements, and it provides a pipelined operation mode. We compare the<jats:italic>time<\/jats:italic>\u00d7<jats:italic>area<\/jats:italic>efficiency for both architectures as well as an RSA application. The systolic implementation can run the 1024 bits RSA decryption process in just 3.23\u2009ms, and the multiplexed architecture executes the same operation in 4.36\u2009ms, but the second approach saves up to 28% of logical resources. These results are competitive with the state-of-the-art performance.<\/jats:p>","DOI":"10.1155\/2011\/127147","type":"journal-article","created":{"date-parts":[[2011,1,5]],"date-time":"2011-01-05T14:49:44Z","timestamp":1294238984000},"page":"1-10","source":"Crossref","is-referenced-by-count":18,"title":["Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation"],"prefix":"10.1155","volume":"2011","author":[{"given":"Guilherme","family":"Perin","sequence":"first","affiliation":[{"name":"Grupo de Microeletr\u00f4nica (GMICRO), Universidade Federal de Santa Maria (UFSM), Rio Grande do Sul, Santa Maria 97105-900, RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Gomes Mesquita","sequence":"additional","affiliation":[{"name":"Arquiteturas, Sistemas Operacionais e Sistemas Distribu\u00eddos, Grupo de Redes (GRASS), Universidade Federal de Uberl\u00e2ndia (UFU), Uberl\u00e2ndia 38401-136, MG, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jo\u00e3o Baptista","family":"Martins","sequence":"additional","affiliation":[{"name":"Grupo de Microeletr\u00f4nica (GMICRO), Universidade Federal de Santa Maria (UFSM), Rio Grande do Sul, Santa Maria 97105-900, RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/359340.359342"},{"key":"10","doi-asserted-by":"crossref","first-page":"519","DOI":"10.1090\/S0025-5718-1985-0777282-X","volume":"44","year":"1985","journal-title":"Mathematics of Computation"},{"issue":"3","key":"16","doi-asserted-by":"crossref","first-page":"376","DOI":"10.1109\/12.210181","volume":"42","year":"1993","journal-title":"IEEE Transactions on Computers"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2006.09.005"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2008.04.013"},{"year":"1951","key":"8"},{"year":"2001","key":"9"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1049\/el:19991230"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1228516"}],"container-title":["International Journal of Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2011\/127147.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2011\/127147.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2011\/127147.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T14:03:34Z","timestamp":1497881014000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.hindawi.com\/journals\/ijrc\/2011\/127147\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"references-count":9,"alternative-id":["127147","127147"],"URL":"https:\/\/doi.org\/10.1155\/2011\/127147","relation":{},"ISSN":["1687-7195","1687-7209"],"issn-type":[{"type":"print","value":"1687-7195"},{"type":"electronic","value":"1687-7209"}],"subject":[],"published":{"date-parts":[[2011]]}}}