{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T21:55:03Z","timestamp":1649022903051},"reference-count":29,"publisher":"Hindawi Limited","license":[{"start":{"date-parts":[[2011,9,15]],"date-time":"2011-09-15T00:00:00Z","timestamp":1316044800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"name":"Department of Science and Technology, Government of India","award":["SR\/FTP\/ETA-063\/2009"],"award-info":[{"award-number":["SR\/FTP\/ETA-063\/2009"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2011,9,15]]},"abstract":"<jats:p>This paper presents a systematic methodology for the generation of high-level performance models for analog component blocks. The transistor sizes of the circuit-level implementations of the component\nblocks along with a set of geometry constraints applied over them define the sample space. A Halton\nsequence generator is used as a sampling algorithm. Performance data are generated by simulating\neach sampled circuit configuration through SPICE. Least squares support vector machine (LS-SVM) is\nused as a regression function. Optimal values of the model hyper parameters are determined through a\ngrid search-based technique and a genetic algorithm- (GA-) based technique. The high-level models of the\nindividual component blocks are combined analytically to construct the high-level model of a complete\nsystem. The constructed performance models have been used to implement a GA-based high-level topology\nsizing process. The advantages of the present methodology are that the constructed models are accurate\nwith respect to real circuit-level simulation results, fast to evaluate, and have a good generalization\nability. In addition, the model construction time is low and the construction process does not require\nany detailed knowledge of circuit design. The entire methodology has been demonstrated with a set\nof numerical results.<\/jats:p>","DOI":"10.1155\/2011\/475952","type":"journal-article","created":{"date-parts":[[2011,9,16]],"date-time":"2011-09-16T02:02:51Z","timestamp":1316138571000},"page":"1-17","source":"Crossref","is-referenced-by-count":0,"title":["A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies"],"prefix":"10.1155","volume":"2011","author":[{"given":"Soumya","family":"Pandit","sequence":"first","affiliation":[{"name":"Institute of Radio Physics and Electronics, University of Calcutta, Kolkata 700009, India"}]},{"given":"Chittaranjan","family":"Mandal","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology, Kharagpur 721302, India"}]},{"given":"Amit","family":"Patra","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology, Kharagpur 721302, India"}]}],"member":"98","reference":[{"key":"1","year":"2008"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045116"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2010.11.004"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2007.06.001"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.02.001"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.925785"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/22.981287"},{"issue":"7","key":"9","doi-asserted-by":"crossref","first-page":"762","DOI":"10.1109\/4.391115","volume":"30","year":"1995","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.854633"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.885734"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/92.994993"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.889371"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/989995.990000"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/43.905671"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/43.905672"},{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.810742"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882513"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2009.09.001"},{"key":"27","year":"2007"},{"key":"28","year":"1998"},{"key":"29","year":"2002"},{"key":"31","year":"1978"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2003.809179"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1016\/S0925-2312(02)00601-X"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1016\/j.ijforecast.2010.02.007"},{"key":"36","year":"2004"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.826329"},{"key":"38","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20000055"},{"key":"39","year":"2004"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2011\/475952.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2011\/475952.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2011\/475952.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,9]],"date-time":"2020-12-09T05:04:47Z","timestamp":1607490287000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2011\/475952\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9,15]]},"references-count":29,"alternative-id":["475952","475952"],"URL":"https:\/\/doi.org\/10.1155\/2011\/475952","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"value":"1065-514X","type":"print"},{"value":"1563-5171","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,9,15]]}}}