{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:31Z","timestamp":1740135931411,"version":"3.37.3"},"reference-count":9,"publisher":"Wiley","license":[{"start":{"date-parts":[[2011,9,15]],"date-time":"2011-09-15T00:00:00Z","timestamp":1316044800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2011,9,15]]},"abstract":"<jats:p>Today's System-on-Chips (SoCs) design is extremely challenging because it involves complicated design tradeoffs and heterogeneous design expertise. To explore the large solution space, system architects have to rely on system-level simulators to identify an optimized SoC architecture. In this paper, we propose a system-level simulation framework, System Performance Simulation Implementation Mechanism, or SPSIM. Based on SystemC TLM2.0, the framework consists of an executable SoC model, a simulation tool chain, and a modeling methodology. Compared with the large body of existing research in this area, this work is aimed at delivering a high simulation throughput and, at the same time, guaranteeing a high accuracy on real industrial applications. Integrating the leading TLM techniques, our simulator can attain a simulation speed that is not slower than that of the hardware execution by a factor of 35 on a set of real-world applications. SPSIM incorporates effective timing models, which can achieve a high accuracy after hardware-based calibration. Experimental results on a set of mobile applications proved that the difference between the simulated and measured results of timing performance is within 10%, which in the past can only be attained by cycle-accurate models.<\/jats:p>","DOI":"10.1155\/2011\/726014","type":"journal-article","created":{"date-parts":[[2011,9,16]],"date-time":"2011-09-16T02:04:18Z","timestamp":1316138658000},"page":"1-17","source":"Crossref","is-referenced-by-count":1,"title":["A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips"],"prefix":"10.1155","volume":"2011","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6971-9684","authenticated-orcid":true,"given":"Guanyi","family":"Sun","sequence":"first","affiliation":[{"name":"Tsinghua-Intel Center of Advanced Mobile Computing, Tsinghua University, Beijing 100084, China"}]},{"given":"Shengnan","family":"Xu","sequence":"additional","affiliation":[{"name":"Tsinghua-Intel Center of Advanced Mobile Computing, Tsinghua University, Beijing 100084, China"},{"name":"Institute of Microelectronics, Tsinghua University, Beijing 100084, China"}]},{"given":"Xu","family":"Wang","sequence":"additional","affiliation":[{"name":"Tsinghua-Intel Center of Advanced Mobile Computing, Tsinghua University, Beijing 100084, China"}]},{"given":"Dawei","family":"Wang","sequence":"additional","affiliation":[{"name":"Tsinghua-Intel Center of Advanced Mobile Computing, Tsinghua University, Beijing 100084, China"}]},{"given":"Eugene","family":"Tang","sequence":"additional","affiliation":[{"name":"Tsinghua-Intel Center of Advanced Mobile Computing, Tsinghua University, Beijing 100084, China"}]},{"given":"Yangdong","family":"Deng","sequence":"additional","affiliation":[{"name":"Tsinghua-Intel Center of Advanced Mobile Computing, Tsinghua University, Beijing 100084, China"},{"name":"Institute of Microelectronics, Tsinghua University, Beijing 100084, China"}]},{"given":"Sun","family":"Chan","sequence":"additional","affiliation":[{"name":"Tsinghua-Intel Center of Advanced Mobile Computing, Tsinghua University, Beijing 100084, China"}]}],"member":"311","reference":[{"year":"2004","series-title":"Systems on Silicon Series","key":"1"},{"year":"2008","series-title":"Systems on Silicon Series","key":"2"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"issue":"4","key":"6","first-page":"52","volume":"26","year":"2006","journal-title":"IEEE Micro Special Issue on Architecture Simulation and Modeling"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/2.982918"},{"issue":"5","key":"21","doi-asserted-by":"crossref","first-page":"12","DOI":"10.1109\/40.621209","volume":"17","year":"1997","journal-title":"IEEE Micro"},{"year":"2008","key":"23"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1145\/1347375.1347378"},{"year":"2003","key":"32"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2011\/726014.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2011\/726014.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2011\/726014.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,9]],"date-time":"2020-12-09T06:19:01Z","timestamp":1607494741000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2011\/726014\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9,15]]},"references-count":9,"alternative-id":["726014","726014"],"URL":"https:\/\/doi.org\/10.1155\/2011\/726014","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2011,9,15]]}}}