{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,12,30]],"date-time":"2022-12-30T00:32:27Z","timestamp":1672360347621},"reference-count":19,"publisher":"Hindawi Limited","license":[{"start":{"date-parts":[[2011,1,1]],"date-time":"2011-01-01T00:00:00Z","timestamp":1293840000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"name":"Austrian FWF Project Theta","award":["P17757"],"award-info":[{"award-number":["P17757"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electrical and Computer Engineering"],"published-print":{"date-parts":[[2011]]},"abstract":"<jats:p>We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply\u2013properties that are considered highly desirable for future technology nodes.<\/jats:p>","DOI":"10.1155\/2011\/936712","type":"journal-article","created":{"date-parts":[[2011,11,1]],"date-time":"2011-11-01T19:02:14Z","timestamp":1320174134000},"page":"1-23","source":"Crossref","is-referenced-by-count":5,"title":["VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation"],"prefix":"10.1155","volume":"2011","author":[{"given":"Gottfried","family":"Fuchs","sequence":"first","affiliation":[{"name":"Embedded Computing Systems Group (E182\/2), Technische Universit\u00e4t Wien, Treitlstra\u00dfe 3, 1040 Vienna, Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Steininger","sequence":"additional","affiliation":[{"name":"Embedded Computing Systems Group (E182\/2), Technische Universit\u00e4t Wien, Treitlstra\u00dfe 3, 1040 Vienna, Austria"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"98","reference":[{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.69"},{"issue":"5","key":"7","doi-asserted-by":"crossref","first-page":"665","DOI":"10.1109\/5.929649","volume":"89","year":"2001","journal-title":"Proceedings of the IEEE"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/4.165336"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803943"},{"issue":"5","key":"13","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1109\/MSPEC.2011.5753229","volume":"48","year":"2011","journal-title":"IEEE of Spectrum"},{"key":"18","first-page":"170","volume":"10","year":"2004","journal-title":"Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/5.362752"},{"key":"27","first-page":"263","volume-title":"The limitations to delay-insensitivity in asynchronous circuits","year":"1990"},{"issue":"2","key":"31","doi-asserted-by":"crossref","first-page":"230","DOI":"10.1016\/0022-0000(86)90028-0","volume":"32","year":"1986","journal-title":"Journal of Computer and System Sciences"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1145\/5383.5384"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1007\/s00446-002-0076-2"},{"key":"36","doi-asserted-by":"publisher","DOI":"10.1145\/28869.28876"},{"key":"37","doi-asserted-by":"publisher","DOI":"10.1007\/s00446-009-0080-x"},{"key":"39","year":"2001"},{"key":"41","doi-asserted-by":"publisher","DOI":"10.1007\/BF01660033"},{"key":"42","doi-asserted-by":"publisher","DOI":"10.1007\/BF01660034"},{"issue":"6","key":"43","doi-asserted-by":"crossref","first-page":"720","DOI":"10.1145\/63526.63532","volume":"32","year":"1989","journal-title":"Communications of the ACM, Turing Award"},{"issue":"2","key":"44","doi-asserted-by":"crossref","first-page":"103","DOI":"10.1016\/0167-9260(92)90001-F","volume":"13","year":"1992","journal-title":"Integration, the VLSI Journal"},{"key":"47","year":"1985"}],"container-title":["Journal of Electrical and Computer Engineering"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2011\/936712.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2011\/936712.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2011\/936712.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T08:55:57Z","timestamp":1497948957000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.hindawi.com\/journals\/jece\/2011\/936712\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"references-count":19,"alternative-id":["936712","936712"],"URL":"https:\/\/doi.org\/10.1155\/2011\/936712","relation":{},"ISSN":["2090-0147","2090-0155"],"issn-type":[{"value":"2090-0147","type":"print"},{"value":"2090-0155","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011]]}}}