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In this paper, we propose a graph\u2010based approach to a stitching algorithm for automatic and optimal scan chain insertion at the RTL. Our method is divided into two main steps. The first one builds graph models for inferring logical proximity information from the design, and then the second one uses classic approximation algorithms for the traveling salesman problem to determine the best scan\u2010stitching ordering. We show how this algorithm allows the decrease of the cost of both scan analysis and implementation, by measuring total wirelength on placed and routed benchmark designs, both academic and industrial.<\/jats:p>","DOI":"10.1155\/2012\/312808","type":"journal-article","created":{"date-parts":[[2012,12,20]],"date-time":"2012-12-20T21:03:53Z","timestamp":1356037433000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["A Graph\u2010Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions"],"prefix":"10.1155","volume":"2012","author":[{"given":"Lilia","family":"Zaourar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yann","family":"Kieffer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chouki","family":"Aktouf","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2012,12,20]]},"reference":[{"volume-title":"Paths, Flows, and VLSI-Layout","year":"1990","author":"Korte B.","key":"e_1_2_7_1_2"},{"volume-title":"Algorithms for VLSI Design Automation","year":"1998","author":"Gerez S. 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