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Application\u2010specific designs have nonuniform network utilization, thereby requiring a buffer\u2010sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage\/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two\u2010phase algorithm to size the switch buffers in network\u2010on\u2010chips (NoCs) considering support for multiple\u2010frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system\u2010on\u2010Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach.<\/jats:p>","DOI":"10.1155\/2012\/537286","type":"journal-article","created":{"date-parts":[[2012,2,28]],"date-time":"2012-02-28T21:03:35Z","timestamp":1330463015000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["A Buffer\u2010Sizing Algorithm for Network\u2010on\u2010Chips with Multiple Voltage\u2010Frequency Islands"],"prefix":"10.1155","volume":"2012","author":[{"given":"Anish S.","family":"Kumar","sequence":"first","affiliation":[]},{"given":"M. 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