{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T14:28:18Z","timestamp":1761488898867,"version":"3.41.2"},"reference-count":30,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2012,4,10]],"date-time":"2012-04-10T00:00:00Z","timestamp":1334016000000},"content-version":"vor","delay-in-days":100,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Journal of Electrical and Computer Engineering"],"published-print":{"date-parts":[[2012,1]]},"abstract":"<jats:p>Abstract models are necessary to assist system architects in the evaluation process of hardware\/software architectures and to cope with the still increasing complexity of embedded systems. Efficient methods are required to create reliable models of system architectures and to allow early performance evaluation and fast exploration of the design space. In this paper, we present a specific transaction level modeling approach for performance evaluation of hardware\/software architectures. This approach relies on a generic execution model that exhibits light modeling effort. Created models are used to evaluate by simulation expected processing and memory resources according to various architectures. The proposed execution model relies on a specific computation method defined to improve the simulation speed of transaction level models. The benefits of the proposed approach are highlighted through two case studies. The first case study is a didactic example illustrating the modeling approach. In this example, a simulation speed\u2010up by a factor of 7,62 is achieved by using the proposed computation method. The second case study concerns the analysis of a communication receiver supporting part of the physical layer of the LTE protocol. In this case study, architecture exploration is led in order to improve the allocation of processing functions.<\/jats:p>","DOI":"10.1155\/2012\/537327","type":"journal-article","created":{"date-parts":[[2012,4,10]],"date-time":"2012-04-10T21:02:01Z","timestamp":1334091721000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A State\u2010Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level"],"prefix":"10.1155","volume":"2012","author":[{"given":"Anthony","family":"Barreteau","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S\u00e9bastien","family":"Le Nours","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Olivier","family":"Pasquier","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2012,4,10]]},"reference":[{"key":"e_1_2_7_1_2","doi-asserted-by":"crossref","unstructured":"van BerkelC. H. Multi-core for mobile phones Proceedings of the Design Automation and Test in Europe Conference and Exhibition (DATE \u203209) April 2009 1260\u20131265 2-s2.0-70350051158.","DOI":"10.1109\/DATE.2009.5090858"},{"key":"e_1_2_7_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.112"},{"key":"e_1_2_7_3_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2004.06.001"},{"key":"e_1_2_7_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.16"},{"key":"e_1_2_7_5_2","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/47580"},{"key":"e_1_2_7_6_2","doi-asserted-by":"publisher","DOI":"10.1007\/b137175"},{"key":"e_1_2_7_7_2","doi-asserted-by":"crossref","unstructured":"GaiL.andlcai@cecs.uci.edu GajskiD. gajski@cecs.uci.edu Transaction level modeling: an overview Proceedings of the 1st IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS \u203203) October 2003 Newport Beach Calif USA 19\u201324.","DOI":"10.1145\/944645.944651"},{"key":"e_1_2_7_8_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-4515-6"},{"key":"e_1_2_7_9_2","unstructured":"Open SystemC Initiative (OSCI) Functional specification for SystemC 2.0 http:\/\/www.systemc.org."},{"key":"e_1_2_7_10_2","unstructured":"Open SystemC Initiative TLM Working Group Transaction Level Modeling Standard 2 (TLM 2) June 2008."},{"key":"e_1_2_7_11_2","doi-asserted-by":"publisher","DOI":"10.1155\/2008\/647953"},{"key":"e_1_2_7_12_2","unstructured":"Soclib: a modelisation and simulation platform for system on chip design 2003 http:\/\/www.soclib.fr."},{"key":"e_1_2_7_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/1457246.1457250"},{"key":"e_1_2_7_14_2","doi-asserted-by":"publisher","DOI":"10.1023\/A:1012231429554"},{"key":"e_1_2_7_15_2","doi-asserted-by":"publisher","DOI":"10.1007\/s10617\u2010006\u20109589\u20104"},{"key":"e_1_2_7_16_2","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/826296"},{"key":"e_1_2_7_17_2","doi-asserted-by":"publisher","DOI":"10.1155\/2008\/712329"},{"key":"e_1_2_7_18_2","unstructured":"Object Management Group (OMG) A UML profile for MARTE beta 1 specification August 2007."},{"key":"e_1_2_7_19_2","doi-asserted-by":"crossref","unstructured":"ViehlA. viehl@fzi.de SanderB. bsander@fzi.de BringmannO. andbringman@fzi.de RosenstielW. rosenstiel@informatik.uni-tuebingen.de Integrated requirement evaluation of non-functional system-on-chip properties Proceedings of the Forum on Specification Verification and Design Languages (FDL\u203208) September 2008 Stuttgart Germany 105\u2013110 https:\/\/doi.org\/10.1109\/FDL.2008.4641430.","DOI":"10.1109\/FDL.2008.4641430"},{"volume-title":"Embedded Real-Time Systems: A Specification and Design Methodology","year":"1993","author":"Calvez J. P.","key":"e_1_2_7_20_2"},{"volume-title":"Modeling Reactive Systems with Statechart","year":"1993","author":"Harel D.","key":"e_1_2_7_21_2"},{"volume-title":"Principles of Digital Design","year":"1996","author":"Gajski D. D.","key":"e_1_2_7_22_2"},{"key":"e_1_2_7_23_2","doi-asserted-by":"crossref","unstructured":"Le NoursS. sebastien.le-nours@univ-nantes.fr BarreteauA. andanthony.barreteau@univ-nantes.fr PasquierO. olivier.pasquier@univ-nantes.fr Modeling technique for simulation time speed-up of performance computation in transaction level models 2010 Proceedings of the Forum of specification and Design Languages (FDL \u203210) September 2010 Southampton UK 136\u2013141 https:\/\/doi.org\/10.1049\/ic.2010.0142.","DOI":"10.1049\/ic.2010.0142"},{"key":"e_1_2_7_24_2","unstructured":"CoFluent Design http:\/\/www.cofluentdesign.com\/."},{"key":"e_1_2_7_25_2","unstructured":"Xilinx. LogiCORE Fast Fourier Transform v7.1. http:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/xfft_ds260.pdf."},{"volume-title":"3G Evolution, HSPA and LTE for Mobile Broadband","year":"2008","author":"Dahlman E.","key":"e_1_2_7_26_2"},{"key":"e_1_2_7_27_2","doi-asserted-by":"crossref","unstructured":"JalierC. LattardD. JerrayaA. A. SassatelliG. BenoitP. andTorresL. Heterogeneous vs homogeneous MPSoC approaches for a mobile LTE modem Proceedings of the Design Automation and Test in Europe Conference and Exhibition (DATE \u203210) March 2010 Dresden Germany 184\u2013189 2-s2.0-77953119086.","DOI":"10.1109\/DATE.2010.5457213"},{"key":"e_1_2_7_28_2","unstructured":"3GPP. TS 36.201 Evolved Universal Terrestrial Radio Access (E-UTRA); LTE physical layer; General description March 2010 http:\/\/www.3gpp.org\/ftp\/Specs\/html\u2010info\/36201.htm."},{"key":"e_1_2_7_29_2","unstructured":"3GPP. TS 36.211 V9.1.0 Evolved Universal Terrestrial Radio Access (E-UTRA); Physical channels and modulation April 2010 http:\/\/www.3gpp.org\/ftp\/specs\/html\u2010info\/36211.htm."},{"key":"e_1_2_7_30_2","doi-asserted-by":"crossref","unstructured":"BerkmannJ. CarbonelliC. DietrichF. DrewesC. andXuW. On 3 G LTE terminal implementation\u2014standard algorithms complexities and challenges Proceedings of the International Wireless Communications and Mobile Computing Conference (IWCMC \u203208) August 2008 970\u2013975 2-s2.0-52949133781 https:\/\/doi.org\/10.1109\/IWCMC.2008.168.","DOI":"10.1109\/IWCMC.2008.168"}],"container-title":["Journal of Electrical and Computer Engineering"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2012\/537327.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2012\/537327.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2012\/537327","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T18:44:51Z","timestamp":1742928291000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2012\/537327"}},"subtitle":[],"editor":[{"given":"Philippe","family":"Coussy","sequence":"additional","affiliation":[],"role":[{"role":"editor","vocabulary":"crossref"}]}],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":30,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,1]]}},"alternative-id":["10.1155\/2012\/537327"],"URL":"https:\/\/doi.org\/10.1155\/2012\/537327","archive":["Portico"],"relation":{},"ISSN":["2090-0147","2090-0155"],"issn-type":[{"type":"print","value":"2090-0147"},{"type":"electronic","value":"2090-0155"}],"subject":[],"published":{"date-parts":[[2012,1]]},"assertion":[{"value":"2011-06-29","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2011-11-20","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-04-10","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"537327"}}