{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:48:34Z","timestamp":1753886914394,"version":"3.41.2"},"reference-count":16,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2012,9,18]],"date-time":"2012-09-18T00:00:00Z","timestamp":1347926400000},"content-version":"vor","delay-in-days":261,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100005710","name":"Universiti Teknologi Petronas","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100005710","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2012,1]]},"abstract":"<jats:p>This paper presents a new architecture for a synchronized frequency multiplier circuit. The proposed architecture is an all\u2010digital dual\u2010loop delay\u2010 and frequency\u2010locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit. Moreover, it can be used in supplying a clock reference for distributed digital processing systems as well as intra\/interchip communication in system\u2010on\u2010chip (SoC). The proposed architecture is designed using the Verilog language and synthesized for the Altera DE2\u201070 development board. The experimental results validate the expected phase tracking as well as the synthesizing properties. For the measurement and validation purpose, an input reference signal in the range of 1.94\u20132.62\u2009MHz was injected; the generated clock signal has a higher frequency, and it is in the range of 124.2\u2013167.9\u2009MHz with a frequency step (i.e., resolution) of 0.168\u2009MHz. The synthesized design requires 330 logic elements using the above Altera board.<\/jats:p>","DOI":"10.1155\/2012\/546212","type":"journal-article","created":{"date-parts":[[2012,9,18]],"date-time":"2012-09-18T21:04:08Z","timestamp":1348002248000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Design of an All\u2010Digital Synchronized Frequency Multiplier Based on a Dual\u2010Loop (D\/FLL) Architecture"],"prefix":"10.1155","volume":"2012","author":[{"given":"Maher","family":"Assaad","sequence":"first","affiliation":[]},{"given":"Mohammed H.","family":"Alser","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2012,9,18]]},"reference":[{"key":"e_1_2_7_1_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2036433"},{"key":"e_1_2_7_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020229"},{"key":"e_1_2_7_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807398"},{"key":"e_1_2_7_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.2011605"},{"key":"e_1_2_7_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.826333"},{"key":"e_1_2_7_6_2","unstructured":"KimB. WeigandtT. C. andGrayP. R. PLL\/DLL system noise analysis for low jitter clock synthesizer design Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS \u203294) June 1994 31\u201334 2-s2.0-0028602549."},{"key":"e_1_2_7_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2008.930152"},{"key":"e_1_2_7_8_2","unstructured":"BaeY. C.andWeiG. Y. A mixed PLL\/DLL architecture for low jitter clock generation Proceedings of the IEEE International Symposium on Cirquits and Systems (ISCAS \u203204) May 2004 V-788\u2013V-791 2-s2.0-4344640510."},{"key":"e_1_2_7_9_2","unstructured":"SayfullahM. Jitter analysis of mixed PLL-DLL architecture in DRAM environment Proceedings of the 16th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES \u203209) June 2009 445\u2013449 2-s2.0-72149116690."},{"key":"e_1_2_7_10_2","doi-asserted-by":"crossref","unstructured":"De PeslouanP. O. L. MajekC. TarisT. DevalY. BelotD. andBegueretJ. B. A new frequency synthesizers stabilization method based on a mixed Phase Locked Loop and Delay Locked Loop architecture Proceedings of the IEEE International Symposium of Circuits and Systems (ISCAS \u203211) May 2011 482\u2013485 2-s2.0-79960879740 https:\/\/doi.org\/10.1109\/ISCAS.2011.5937607.","DOI":"10.1109\/ISCAS.2011.5937607"},{"key":"e_1_2_7_11_2","doi-asserted-by":"publisher","DOI":"10.1587\/elex.8.2017"},{"key":"e_1_2_7_12_2","doi-asserted-by":"crossref","unstructured":"StefoR. SchreiterJ. SchlusslerJ.-U. andSchuffnyR. High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications Proceedings of the IEEE International Conference in Field-Programmable Technology (FPT \u203203) 2003 28\u201334.","DOI":"10.1109\/FPT.2003.1275728"},{"volume-title":"Phase-Locked Loop Circuit Design","year":"1991","author":"Wolaver D. H.","key":"e_1_2_7_13_2"},{"key":"e_1_2_7_14_2","unstructured":"LinF. Research and design of low jitter wide locking-range all-digital phase-locked and delay-locked loops [Ph.D. dissertation] 2000."},{"key":"e_1_2_7_15_2","unstructured":"MoorthiS. MeganathanD. JanarthananD. Praveen KumarP. andRaja Paul PerinbamJ. Low jitter ADPLL based clock generatorfor high speed SoC applications 32 Proceedings of The World Academy of Science Engineering and Technology August 2008."},{"key":"e_1_2_7_16_2","unstructured":"GudeM.andMuellerG. Mixed signal IP: fully digital implemented phase locked loop IP Based SoC Design Conference December 2006."}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2012\/546212.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2012\/546212.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2012\/546212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,9]],"date-time":"2025-04-09T00:43:44Z","timestamp":1744159424000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2012\/546212"}},"subtitle":[],"editor":[{"given":"Antonio G. M.","family":"Strollo","sequence":"additional","affiliation":[]}],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":16,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,1]]}},"alternative-id":["10.1155\/2012\/546212"],"URL":"https:\/\/doi.org\/10.1155\/2012\/546212","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2012,1]]},"assertion":[{"value":"2012-03-02","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-05-22","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-09-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"546212"}}