{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:02:51Z","timestamp":1761580971258,"version":"3.41.2"},"reference-count":27,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2012,3,29]],"date-time":"2012-03-29T00:00:00Z","timestamp":1332979200000},"content-version":"vor","delay-in-days":88,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/100011102","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["248424"],"award-info":[{"award-number":["248424"]}],"id":[{"id":"10.13039\/100011102","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2012,1]]},"abstract":"<jats:p>Application Specific Instruction\u2010set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and rapid simulation tools are needed to explore the design space. To this aim, FPGA\u2010based emulators have recently been proposed as an alternative to pure software cycle\u2010accurate simulator. However, the advantages of on\u2010hardware emulation are reduced by the overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in this paper aims at mitigating this overhead, exploiting a form of software\u2010driven platform runtime reconfiguration. We present a complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned architecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The approach has been validated against two different case studies, a filtering kernel and an M\u2010JPEG encoding kernel. Moreover, the presented emulation toolchain couples FPGA emulation with activity\u2010based physical modeling to extract area and power\/energy consumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration time, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.<\/jats:p>","DOI":"10.1155\/2012\/580584","type":"journal-article","created":{"date-parts":[[2012,3,29]],"date-time":"2012-03-29T21:03:40Z","timestamp":1333055020000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["Enabling Fast ASIP Design Space Exploration: An FPGA\u2010Based Runtime Reconfigurable Prototyper"],"prefix":"10.1155","volume":"2012","author":[{"given":"Paolo","family":"Meloni","sequence":"first","affiliation":[]},{"given":"Sebastiano","family":"Pomata","sequence":"additional","affiliation":[]},{"given":"Giuseppe","family":"Tuveri","sequence":"additional","affiliation":[]},{"given":"Simone","family":"Secchi","sequence":"additional","affiliation":[]},{"given":"Luigi","family":"Raffo","sequence":"additional","affiliation":[]},{"given":"Menno","family":"Lindwer","sequence":"additional","affiliation":[]}],"member":"311","published-online":{"date-parts":[[2012,3,29]]},"reference":[{"volume-title":"Hivelogic Configurable Parallel Processing Platform","year":"2010","author":"SiliconHive","key":"e_1_2_10_1_2"},{"key":"e_1_2_10_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"e_1_2_10_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"e_1_2_10_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_10_5_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11265\u2010005\u20106648\u20101"},{"key":"e_1_2_10_6_2","doi-asserted-by":"crossref","unstructured":"MillerJ. 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