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However, design effort for FPGA implementations remains high\u2014often an order of magnitude larger than design effort using high\u2010level languages. Instead of this time\u2010consuming process, high\u2010level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C\/C++ and SystemC. Such tools reduce design effort: high\u2010level descriptions are more compact and less error prone. HLS tools promise hardware development abstracted from software designer knowledge of the implementation platform. In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state\u2010of\u2010the\u2010art HLS tool). In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels. Then, to evaluate the suitability of HLS on real\u2010world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition. Based on our study, we provide insights on current limitations of mapping general\u2010purpose software to hardware using HLS and some future directions for HLS tool development. We also offer several guidelines for hardware\u2010friendly software design. For popular embedded benchmark kernels, the designs produced by HLS achieve 4X to 126X speedup over the software version. The stereo matching algorithms achieve between 3.5X and 67.9X speedup over software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.<\/jats:p>","DOI":"10.1155\/2012\/649057","type":"journal-article","created":{"date-parts":[[2012,2,7]],"date-time":"2012-02-07T21:01:20Z","timestamp":1328648480000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":59,"title":["High\u2010Level Synthesis: Productivity, Performance, and Software Constraints"],"prefix":"10.1155","volume":"2012","author":[{"given":"Yun","family":"Liang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyle","family":"Rupnow","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yinan","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dongbo","family":"Min","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minh N.","family":"Do","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deming","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2012,2,7]]},"reference":[{"key":"e_1_2_9_1_2","doi-asserted-by":"publisher","DOI":"10.1145\/1754386.1754387"},{"key":"e_1_2_9_2_2","doi-asserted-by":"crossref","unstructured":"HeC. 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