{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,30]],"date-time":"2025-07-30T14:47:14Z","timestamp":1753886834854,"version":"3.41.2"},"reference-count":84,"publisher":"Wiley","issue":"1","license":[{"start":{"date-parts":[[2012,6,26]],"date-time":"2012-06-26T00:00:00Z","timestamp":1340668800000},"content-version":"vor","delay-in-days":177,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2012,1]]},"abstract":"<jats:p>Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low\u2010density parity\u2010check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state\u2010of\u2010the\u2010art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.<\/jats:p>","DOI":"10.1155\/2012\/730835","type":"journal-article","created":{"date-parts":[[2012,6,27]],"date-time":"2012-06-27T14:54:55Z","timestamp":1340808895000},"update-policy":"https:\/\/doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Flexible LDPC Decoder Architectures"],"prefix":"10.1155","volume":"2012","author":[{"given":"Muhammad","family":"Awais","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carlo","family":"Condo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2012,6,26]]},"reference":[{"key":"e_1_2_7_1_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2005.861013"},{"key":"e_1_2_7_2_2","doi-asserted-by":"crossref","unstructured":"L\u00f6rinczJ.andBegu\u0161i\u0107D. Physical layer analysis of emerging IEEE 802.11n WLAN standard Proceedings of the 8th International Conference Advanced Communication Technology (ICACT \u203206) February 2006 189\u2013194 2-s2.0-33750951007.","DOI":"10.1109\/ICACT.2006.205949"},{"key":"e_1_2_7_3_2","unstructured":"The IEEE p802.3an 10GBASE-T task force http:\/\/www.ieee802.org\/3\/an\/."},{"key":"e_1_2_7_4_2","unstructured":"IEEE standard for local and metropolitan area networks part 16: Air interface for fixed and mobile broadband wireless access systems amendment 2: physical and medium access control layers for combined fixed and mobile operation in licensed bands and corrigendum 1 IEEE Std 802.16e-2005 and IEEE Std 802.16-2004\/Cor 1-2005 (Amendment and Corrigendum to IEEE Std 802.16-2004) 2006."},{"key":"e_1_2_7_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1962.1057683"},{"key":"e_1_2_7_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1981.1056404"},{"key":"e_1_2_7_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864133"},{"key":"e_1_2_7_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/18.910572"},{"key":"e_1_2_7_9_2","doi-asserted-by":"crossref","first-page":"1098","DOI":"10.1049\/ip-com:20050205","article-title":"Finite precision implementation of LDPC decoders","volume":"152","author":"Masera G.","year":"2005","journal-title":"IEE Proceedings on Communications"},{"key":"e_1_2_7_10_2","unstructured":"WibergN. Codes and decoding on general graphs Ph.D. dissertation 1996 Linkoping University Linkoping Sweden."},{"key":"e_1_2_7_11_2","doi-asserted-by":"crossref","unstructured":"DaudM. SuksmonoA. Hendrawan andSugihartono Comparison of decoding algorithms for LDPC codes of IEEE 802.16e standard Proceedings of the 6th International Conference on Telecommunication Systems Services and Applications (TSSA \u203211) October 2011 280\u2013283.","DOI":"10.1109\/TSSA.2011.6095450"},{"key":"e_1_2_7_12_2","unstructured":"ChenJ.andFossorierM. P. C. Near optimum universal belief propagation based decoding of LDPC codes and extension to turbo decoding Proceedings of the IEEE International Symposium on Information Theory (ISIT \u203201) June 2001 2-s2.0-0034858616."},{"key":"e_1_2_7_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2005.852852"},{"key":"e_1_2_7_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2011.2173045"},{"key":"e_1_2_7_15_2","doi-asserted-by":"crossref","unstructured":"YeoE. PakzadP. Nikoli\u0107B. andAnantharamV. High throughput low-density parity-check decoder architectures Proceedings of the IEEE Global Telecommunicatins Conference (GLOBECOM \u203201) November 2001 3019\u20133024 2-s2.0-0035685606.","DOI":"10.1109\/GLOCOM.2001.965981"},{"key":"e_1_2_7_16_2","doi-asserted-by":"crossref","unstructured":"MansourM.andShanbhagN. Memory-efficient turbo decoder architectures for LDPC codes Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS \u203202) October 2002 159\u2013164.","DOI":"10.1109\/SIPS.2002.1049702"},{"key":"e_1_2_7_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1974.1055186"},{"key":"e_1_2_7_18_2","doi-asserted-by":"crossref","unstructured":"ZhangJ.andFossorierM. Shuffled belief propagation decoding 1 Proceedings of the 36th Asilomar Conference on Signals Systems and Computers November 2002 8\u201315 2-s2.0-0038304877.","DOI":"10.1109\/ACSSC.2002.1197141"},{"key":"e_1_2_7_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2004.838370"},{"key":"e_1_2_7_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/4.987093"},{"key":"e_1_2_7_21_2","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e89\u2010a.7.1976"},{"key":"e_1_2_7_22_2","doi-asserted-by":"crossref","unstructured":"NagarajanV. JayakumarN. KhatriS. andMilenkovi\u00e7O. High-throughput VLSI implementations of iterative decoders and related code construction problems 1 Proceedings of the IEEE Global Telecommunications Conference (GLOBECOM \u203204) December 2004 361\u2013365 2-s2.0-18144419713.","DOI":"10.1109\/GLOCOM.2004.1377970"},{"key":"e_1_2_7_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2007.906890"},{"key":"e_1_2_7_24_2","doi-asserted-by":"crossref","unstructured":"LechnerG. SayirJ. andRuppM. Efficient DSP implementation of an LDPC decoder 4 Proceedings of the IEEE International Conference on Acoustics Speech and Signal Processing May 2004 V-665\u2013V-668 2-s2.0-4544257960.","DOI":"10.1109\/ICASSP.2004.1326914"},{"key":"e_1_2_7_25_2","unstructured":"ZhangT.andParhiK. A 54 Mbps (3 6)-regular FPGA LDPC decoder Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS \u201902) October 2002 127\u2013132."},{"key":"e_1_2_7_26_2","unstructured":"BoutillonE. CasturaJ. andKschichangF. Decoder first code desig Proceedings of the 2nd International Symposium on Turbo Codes and Related Topics September 2000 459\u2013462."},{"key":"e_1_2_7_27_2","doi-asserted-by":"crossref","unstructured":"BrackT. AllesM. KienleF. andWehnN. A synthesizable IP core for WiMax 802.16E LDPC code decoding Proceedings of the 17th International Symposium on Personal Indoor and Mobile Radio Communications (PIMRC \u203206) September 2006 1\u20135 2-s2.0-44949131613 https:\/\/doi.org\/10.1109\/PIMRC.2006.254126.","DOI":"10.1109\/PIMRC.2006.254126"},{"key":"e_1_2_7_28_2","doi-asserted-by":"crossref","unstructured":"BrackT. AllesM. Lehnigk-EmdenT. KienleF. WehnN. L\u2032InsalataN. E. RossiF. RoviniM. andFanucciL. Low complexity LDPC code decoders for next generation standards Proceedings of the Design Automation and Test in Europe Conference and Exhibition (DATE \u203207) April 2007 331\u2013336 2-s2.0-34548336878 https:\/\/doi.org\/10.1109\/DATE.2007.364613.","DOI":"10.1109\/DATE.2007.364613"},{"key":"e_1_2_7_29_2","doi-asserted-by":"crossref","unstructured":"AllesM. WehnN. andBerensF. A synthesizable IP core for WiMedia 1.5 UWB LDPC code decoding Proceedings of the IEEE International Conference on Ultra-Wideband (ICUWB \u203209) September 2009 597\u2013601 2-s2.0-71949122209 https:\/\/doi.org\/10.1109\/ICUWB.2009.5288833.","DOI":"10.1109\/ICUWB.2009.5288833"},{"key":"e_1_2_7_30_2","doi-asserted-by":"crossref","unstructured":"ZhangB. LiuH. ChenX. LiuD. andYiX. Low complexity DVB-S2 LDPC decoder Proceedings of the 69th IEEE Vehicular Technology Conference (VTC \u203209) April 2009 1\u20135 2-s2.0-70349665172 https:\/\/doi.org\/10.1109\/VETECS.2009.5073653.","DOI":"10.1109\/VETECS.2009.5073653"},{"key":"e_1_2_7_31_2","doi-asserted-by":"crossref","unstructured":"ChoJ. ShanbhagN. R. andSungW. Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS \u203209) October 2009 40\u201345 2-s2.0-74549139694 https:\/\/doi.org\/10.1109\/SIPS.2009.5336223.","DOI":"10.1109\/SIPS.2009.5336223"},{"key":"e_1_2_7_32_2","doi-asserted-by":"crossref","unstructured":"KuoT. C.andWillsonA. N. A flexible decoder IC for WiMAX QC-LDPC codes Proceedings of the IEEE Custom Integrated Circuits Conference (CICC \u203208) September 2008 527\u2013530 2-s2.0-57849159398 https:\/\/doi.org\/10.1109\/CICC.2008.4672138.","DOI":"10.1109\/CICC.2008.4672138"},{"key":"e_1_2_7_33_2","doi-asserted-by":"crossref","unstructured":"HuangS. BaoD. XiangB. ChenY. andZengX. A flexible LDPC decoder architecture supporting two decoding algorithms Proceedings of the IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (ISCAS \u203210) June 2010 3929\u20133932 2-s2.0-77955998589 https:\/\/doi.org\/10.1109\/ISCAS.2010.5537686.","DOI":"10.1109\/ISCAS.2010.5537686"},{"key":"e_1_2_7_34_2","doi-asserted-by":"crossref","unstructured":"XiangB. BaoD. HuangS. andZengX. A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications Proceedings of the 21st IEEE International Conference on Application-Specific Systems Architectures and Processors (ASAP \u203210) July 2010 225\u2013232 2-s2.0-77955885261 https:\/\/doi.org\/10.1109\/ASAP.2010.5540958.","DOI":"10.1109\/ASAP.2010.5540958"},{"key":"e_1_2_7_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2071910"},{"key":"e_1_2_7_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.916610"},{"key":"e_1_2_7_37_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.916606"},{"key":"e_1_2_7_38_2","doi-asserted-by":"crossref","unstructured":"ShihX. Y. ZhanC. Z. andWuA. Y. A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC \u203209) November 2009 369\u2013372 2-s2.0-76249091354 https:\/\/doi.org\/10.1109\/ASSCC.2009.5357173.","DOI":"10.1109\/ASSCC.2009.5357173"},{"key":"e_1_2_7_39_2","unstructured":"MurugappaP. Al-KhayatR. BaghdadiA. andJezequelM. A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding Proceedings of the 14th Design Automation and Test in Europe Conference and Exhibition (DATE \u203211) March 2011 228\u2013233 2-s2.0-79957552633."},{"key":"e_1_2_7_40_2","doi-asserted-by":"crossref","unstructured":"ScarpellinoM. SinghA. BoutillonE. andMaseraG. Reconfigurable architecture for LDPC and turbo decoding: a NoC case study Proceedings of the 10th International Symposium on Spread Spectrum Techniques and Applications (ISSSTA \u203208) August 2008 671\u2013676 2-s2.0-57849167109 https:\/\/doi.org\/10.1109\/ISSSTA.2008.131.","DOI":"10.1109\/ISSSTA.2008.131"},{"key":"e_1_2_7_41_2","doi-asserted-by":"crossref","unstructured":"AllesM. VogtT. andWehnN. FlexiChaP: a reconfigurable ASIP for convolutional turbo and LDPC code decoding Proceedings of the 5th International Symposium on Turbo Codes and Related Topics (TURBOCODING \u203208) September 2008 84\u201389 2-s2.0-57849133630 https:\/\/doi.org\/10.1109\/TURBOCODING.2008.4658677.","DOI":"10.1109\/TURBOCODING.2008.4658677"},{"key":"e_1_2_7_42_2","doi-asserted-by":"crossref","unstructured":"NaessensF. BourdouxA. andDejongheA. A flexible ASIP decoder for combined binary and non-binary LDPC codes Proceedings of the 17th IEEE Symposium on Communications and Vehicular Technology in the Benelux (SCVT \u20322010) November 2010 1\u20135 2-s2.0-79952829707 https:\/\/doi.org\/10.1109\/SCVT.2010.5720462.","DOI":"10.1109\/SCVT.2010.5720462"},{"key":"e_1_2_7_43_2","unstructured":"GuilloudF. BoutillonE. andDangerJ. \u03bb-min decoding algorithm of regular and irregular LDPC codes Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics September 2003 451\u2013454."},{"key":"e_1_2_7_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.922024"},{"key":"e_1_2_7_45_2","unstructured":"CastanoM. RoviniM. L\u2019InsalataN.E. RossiF. MerlinoR. CiofiC. andFanucciL. Adaptive single phase decoding of LDPC codes Proceedings of the 6th International ITG-Conference on Source and Channel Coding (TURBOCODING) 4th International Symposium on Turbo Codes&Related Topics April 2006 1\u20136."},{"key":"e_1_2_7_46_2","doi-asserted-by":"crossref","unstructured":"ParkI. C.andKangS. H. Scheduling algorithm for partially parallel architecture of ldpc decoder by matrix permutation 6 Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS \u203205) May 2005 5778\u20135781 2-s2.0-33750918495 https:\/\/doi.org\/10.1109\/ISCAS.2005.1465951.","DOI":"10.1109\/ISCAS.2005.1465951"},{"key":"e_1_2_7_47_2","doi-asserted-by":"crossref","unstructured":"GunnamK. ChoiG. andYearyM. A parallel VLSI architecture for layered decoding for array LDPC codes Proceedings of the 6th International Conference on Embedded Systems 20th International Conference on VLSI Design January 2007 738\u2013743.","DOI":"10.1109\/VLSID.2007.19"},{"key":"e_1_2_7_48_2","unstructured":"High Rate UWB PHY and MAC Standard Standard ECMA-368 Std http:\/\/www.ecma\u2010international.org."},{"key":"e_1_2_7_49_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.821775"},{"key":"e_1_2_7_50_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.826201"},{"key":"e_1_2_7_51_2","doi-asserted-by":"crossref","unstructured":"VogtT.andWehnN. A Reconfigurable application specific instruction set processor for convolutional and turbo decoding in a SDR environment Proceedings of the Design Automation and Test in Europe (DATE \u203208) March 2008 38\u201343 2-s2.0-49749125947 https:\/\/doi.org\/10.1109\/DATE.2008.4484657.","DOI":"10.1109\/DATE.2008.4484657"},{"key":"e_1_2_7_52_2","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1966.5273"},{"key":"e_1_2_7_53_2","doi-asserted-by":"crossref","unstructured":"AwaisM. SinghA. BoutillonE. andMaseraG. A novel architecture for scalable high throughput multi-standard LDPC decoder 31 Proceedings of the 14th Euromicro Conference on Digital System Design (DSD \u203211) September 2011 340\u2013347.","DOI":"10.1109\/DSD.2011.112"},{"key":"e_1_2_7_54_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002487"},{"key":"e_1_2_7_55_2","doi-asserted-by":"publisher","DOI":"10.1049\/el:20071157"},{"key":"e_1_2_7_56_2","doi-asserted-by":"crossref","unstructured":"QuaglioF. VaccaF. CastellanoC. TarableA. andMaseraG. Interconnection framework for high-throughput flexible LDPC decoders Proceedings of the Design Automation and Test in Europe (DATE \u203206) March 2006 2-s2.0-34047111317.","DOI":"10.1109\/DATE.2006.243815"},{"key":"e_1_2_7_57_2","doi-asserted-by":"crossref","unstructured":"GunnamK. K. ChoiG. S. YearyM. B. andAtiquzzamanM. VLSI architectures for layered decoding for irregular LDPC codes of WiMax Proceedings of the IEEE International Conference on Communications (ICC \u203207) June 2007 4542\u20134547 2-s2.0-38549086489 https:\/\/doi.org\/10.1109\/ICC.2007.750.","DOI":"10.1109\/ICC.2007.750"},{"key":"e_1_2_7_58_2","doi-asserted-by":"crossref","unstructured":"DielissenJ. HekstraA. andBergV. Low cost LDPC decoder for DVB-S2 2 Proceedings of the Design Automation and Test in Europe (DATE \u203206) March 2006 1\u20136 2-s2.0-34047224809.","DOI":"10.1109\/DATE.2006.243816"},{"key":"e_1_2_7_59_2","doi-asserted-by":"crossref","unstructured":"KarkootiM. RadosavljevicP. andCavallaroJ. R. Configurable high throughput irregular LDPC decoder architecture: tradeoff analysis and implementation Proceedings of the 17th IEEE International Conference on Application-Specific Systems Architectures and Processors (ASAP \u203206) September 2006 360\u2013367 2-s2.0-34547398974 https:\/\/doi.org\/10.1109\/ASAP.2006.23.","DOI":"10.1109\/ASAP.2006.23"},{"key":"e_1_2_7_60_2","doi-asserted-by":"crossref","first-page":"116","DOI":"10.1109\/TCSI.2009.2018915","article-title":"Flexible LDPC decoder design for multigigabit-per-second applications","volume":"57","author":"Zhang C.","year":"2010","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"key":"e_1_2_7_61_2","doi-asserted-by":"crossref","unstructured":"GentileG. RoviniM. andFanucciL. A multi-standard flexible Turbo\/LDPC decoder via ASIC design Proceedings of the 6th International Symposium on Turbo Codes and Iterative Information Processing (ISTC \u203210) September 2010 294\u2013298 2-s2.0-78649256060 https:\/\/doi.org\/10.1109\/ISTC.2010.5613886.","DOI":"10.1109\/ISTC.2010.5613886"},{"key":"e_1_2_7_62_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2004.833353"},{"key":"e_1_2_7_63_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2007736"},{"key":"e_1_2_7_64_2","doi-asserted-by":"crossref","unstructured":"TangJ. BhattT. SundaramurthyV. andParhiK. K. Reconfigurable shuffle network design in LDPC decoders Proceedings of the 17th IEEE International Conference on Application-Specific Systems Architectures and Processors (ASAP \u203206) September 2006 81\u201386 2-s2.0-34547406193 https:\/\/doi.org\/10.1109\/ASAP.2006.60.","DOI":"10.1109\/ASAP.2006.60"},{"key":"e_1_2_7_65_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2015353"},{"key":"e_1_2_7_66_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2027967"},{"volume-title":"Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes","year":"1992","author":"Leighton F. T.","key":"e_1_2_7_67_2"},{"key":"e_1_2_7_68_2","doi-asserted-by":"crossref","unstructured":"PengX. ChenZ. ZhaoX. MaeharaF. andGotoS. High parallel variation banyan network based permutation network for reconfigurable LDPC decoder Proceedings of the 21st IEEE International Conference on Application-Specific Systems Architectures and Processors (ASAP \u203210) July 2010 233\u2013238 2-s2.0-77955901732 https:\/\/doi.org\/10.1109\/ASAP.2010.5540964.","DOI":"10.1109\/ASAP.2010.5540964"},{"key":"e_1_2_7_69_2","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_2_7_70_2","doi-asserted-by":"crossref","unstructured":"MoussaH. BaghdadiA. andJ\u00e9z\u00e9quelM. Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder Proceedings of the 45th Design Automation Conference (DAC \u203208) June 2008 429\u2013434 2-s2.0-51549115118 https:\/\/doi.org\/10.1109\/DAC.2008.4555856.","DOI":"10.1145\/1391469.1391582"},{"key":"e_1_2_7_71_2","first-page":"758","article-title":"A combinatorial problem","volume":"49","author":"De Bruijn N.","year":"1946","journal-title":"Koninklijke Nederlandse Akademie"},{"key":"e_1_2_7_72_2","doi-asserted-by":"crossref","unstructured":"TheocharidesT. LinkG. VijaykrishnanN. andIrwinM. J. Implementing LDPC decoding on network-on-chip Proceedings of the 18th International Conference on VLSI Design: Power Aware Design of VLSI Systems January 2005 134\u2013137 2-s2.0-27944498512.","DOI":"10.1109\/ICVD.2005.109"},{"key":"e_1_2_7_73_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.894409"},{"key":"e_1_2_7_74_2","unstructured":"KienleF. ThulM. andWhenN. Implementation issues of scalable LDPC-decoders Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics 2003."},{"key":"e_1_2_7_75_2","unstructured":"SeoD. AliA. LimW. T. RafiqueN. andThottethodiM. Near-optimal worst-case throughput routing for two-dimensional mesh networks Proceedings of the 32nd Interntional Symposium on Computer Architecture (ISCA \u203205) June 2005 432\u2013443 2-s2.0-27544463701."},{"key":"e_1_2_7_76_2","doi-asserted-by":"crossref","unstructured":"VaccaF. MaseraG. MoussaH. BaghdadiA. andJezequelM. Flexible architectures for LDPC decoders based on network on chip paradigm Proceedings of the 12th Euromicro Conference on Digital System Design: Architectures Methods and Tools (DSD \u203209) August 2009 582\u2013589 2-s2.0-74549226214 https:\/\/doi.org\/10.1109\/DSD.2009.235.","DOI":"10.1109\/DSD.2009.235"},{"key":"e_1_2_7_77_2","doi-asserted-by":"crossref","unstructured":"HocevarD. E. A reduced complexity decoder architecture via layered decoding of LDPC codes Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation October 2004 107\u2013112 2-s2.0-17044383428.","DOI":"10.1109\/SIPS.2004.1363033"},{"key":"e_1_2_7_78_2","unstructured":"CondoC. A parallel LDPC decoder with Network on Chip as underlying architecture M.S. thesis 2010 Politecnico di Torino."},{"key":"e_1_2_7_79_2","doi-asserted-by":"crossref","unstructured":"CondoC.andMaseraG. A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP \u203211) November 2011 1\u20138.","DOI":"10.1109\/DASIP.2011.6136889"},{"key":"e_1_2_7_80_2","doi-asserted-by":"crossref","unstructured":"ChenZ. ZhaoX. PengX. ZhouD. andGotoS. An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards Proceedings of the IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (ISCAS \u203210) June 2010 473\u2013476 2-s2.0-77955999308 https:\/\/doi.org\/10.1109\/ISCAS.2010.5537638.","DOI":"10.1109\/ISCAS.2010.5537638"},{"key":"e_1_2_7_81_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2046257"},{"key":"e_1_2_7_82_2","doi-asserted-by":"crossref","unstructured":"CondoC. MartinaM. andMaseraG. A Network-on-Chip-based high throughput turbo\/LDPC decoder architecture Proceedings of the Conference on Design Automation and Test in Europe (DATE \u203212) 2012.","DOI":"10.1109\/DATE.2012.6176715"},{"key":"e_1_2_7_83_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676323"},{"key":"e_1_2_7_84_2","doi-asserted-by":"crossref","unstructured":"NaessensF. BougardB. BressinckS. HollevoetL. RaghavanP. Van PerreL. D. andCatthoorF. A unified instruction set programmable architecture for multi-standard advanced forward error correction Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS \u203208) October 2008 31\u201336 2-s2.0-57849119284 https:\/\/doi.org\/10.1109\/SIPS.2008.4671733.","DOI":"10.1109\/SIPS.2008.4671733"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2012\/730835.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2012\/730835.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1155\/2012\/730835","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,2]],"date-time":"2025-04-02T19:05:43Z","timestamp":1743620743000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1155\/2012\/730835"}},"subtitle":[],"editor":[{"given":"Amer","family":"Baghdadi","sequence":"additional","affiliation":[],"role":[{"role":"editor","vocabulary":"crossref"}]}],"short-title":[],"issued":{"date-parts":[[2012,1]]},"references-count":84,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,1]]}},"alternative-id":["10.1155\/2012\/730835"],"URL":"https:\/\/doi.org\/10.1155\/2012\/730835","archive":["Portico"],"relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2012,1]]},"assertion":[{"value":"2011-11-04","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-02-22","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2012-06-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}],"article-number":"730835"}}