{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T14:57:06Z","timestamp":1740149826441,"version":"3.37.3"},"reference-count":6,"publisher":"Wiley","license":[{"start":{"date-parts":[[2012,1,1]],"date-time":"2012-01-01T00:00:00Z","timestamp":1325376000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["International Journal of Reconfigurable Computing"],"published-print":{"date-parts":[[2012]]},"abstract":"<jats:p>In the rate-distortion optimization (RDO), the process of choosing the best prediction mode is performed through exhaustive executions of the whole encoding process, increasing significantly the encoder computational complexity. Considering H.264\/AVC intra frame prediction, there are several modes to encode a macroblock (MB). This work proposes an algorithm and the hardware design for a fast intra frame mode decision module for H.264\/AVC encoders. The application of the proposed algorithm reduces in more than 10 times the number of encoding iterations for choosing the best intramode when compared with RDO-based decision. The architecture was synthesized to FPGA and achieved an operation frequency of 98\u2009MHz processing more than 300\u2009HD1080p frames per second. With this approach, we achieved one order-of-magnitude performance improvement compared with RDO-based approaches, which is very important not only from the performance but also from the energy consumption perspective for battery-operated devices. In order to compare the architecture with previously published works, we also synthesized it to standard cells. Compared with the best previous results reported, the implemented architecture achieves a complexity reduction of five times, a processing capability increase of 14 times, and a reduction in the number of clock cycles per MB of 11 times.<\/jats:p>","DOI":"10.1155\/2012\/813023","type":"journal-article","created":{"date-parts":[[2012,9,2]],"date-time":"2012-09-02T17:01:20Z","timestamp":1346605280000},"page":"1-10","source":"Crossref","is-referenced-by-count":2,"title":["Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264\/AVC Encoders"],"prefix":"10.1155","volume":"2012","author":[{"given":"Daniel","family":"Palomino","sequence":"first","affiliation":[{"name":"Microelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gon\u00e7alves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, Brazil"}]},{"given":"Guilherme","family":"Corr\u00eaa","sequence":"additional","affiliation":[{"name":"Microelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gon\u00e7alves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, Brazil"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5019-3715","authenticated-orcid":true,"given":"Cl\u00e1udio","family":"Diniz","sequence":"additional","affiliation":[{"name":"Microelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gon\u00e7alves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, Brazil"}]},{"given":"Sergio","family":"Bampi","sequence":"additional","affiliation":[{"name":"Microelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gon\u00e7alves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, Brazil"}]},{"given":"Luciano","family":"Agostini","sequence":"additional","affiliation":[{"name":"Group of Architectures and Integrated Circuits, CDTEC, Federal University of Pelotas, Campus Universit\u00e1rio s\/n, P.O. Box 354, 96001-970 Pelotas, RS, Brazil"}]},{"given":"Altamiro","family":"Susin","sequence":"additional","affiliation":[{"name":"Microelectronics Group, INF, Federal University of Rio Grande do Sul, Avenida Bento Gon\u00e7alves 9500, P.O. Box 15064, 91501-970 Porto Alegre, RS, Brazil"}]}],"member":"311","reference":[{"issue":"6","key":"2","doi-asserted-by":"crossref","first-page":"74","DOI":"10.1109\/79.733497","volume":"15","year":"1998","journal-title":"IEEE Signal Processing Magazine"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2007.903786"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2009.2013511"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2008.4711266"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2010.2057018"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2003.815165"}],"container-title":["International Journal of Reconfigurable Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2012\/813023.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2012\/813023.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/ijrc\/2012\/813023.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T19:34:04Z","timestamp":1497987244000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.hindawi.com\/journals\/ijrc\/2012\/813023\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012]]},"references-count":6,"alternative-id":["813023","813023"],"URL":"https:\/\/doi.org\/10.1155\/2012\/813023","relation":{},"ISSN":["1687-7195","1687-7209"],"issn-type":[{"type":"print","value":"1687-7195"},{"type":"electronic","value":"1687-7209"}],"subject":[],"published":{"date-parts":[[2012]]}}}