{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:04:39Z","timestamp":1740135879250,"version":"3.37.3"},"reference-count":8,"publisher":"Wiley","license":[{"start":{"date-parts":[[2013,1,15]],"date-time":"2013-01-15T00:00:00Z","timestamp":1358208000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2013,1,15]]},"abstract":"<jats:p>In this paper, we present and compare efficient low-power hardware architectures for accelerating the Packet Data Convergence Protocol (PDCP) in LTE and LTE-Advanced mobile terminals. Specifically, our work proposes the design of two cores: a crypto engine for the Evolved Packet System Encryption Algorithm (128-EEA2) that is based on the AES cipher and a coprocessor for the Least Significant Bit (LSB) encoding mechanism of the Robust Header Compression (ROHC) algorithm. With respect to the former, first we propose a reference architecture, which reflects a basic implementation of the algorithm, then we identify area and power bottle-necks in the design and finally we introduce and compare several architectures targeting the most power-consuming operations. With respect to the LSB coprocessor, we propose a novel implementation based on a one-hot encoding, thereby reducing hardware\u2019s logic switching rate. Architectural hardware analysis is performed using Faraday\u2019s 90\u2009nm standard-cell library. The obtained results, when compared against the reference architecture, show that these novel architectures achieve significant improvements, namely, 25% in area and 35% in power consumption for the 128-EEA2 crypto-core, and even more important reductions are seen for the LSB coprocessor, that is, 36% in area and 50% in power consumption.<\/jats:p>","DOI":"10.1155\/2013\/369627","type":"journal-article","created":{"date-parts":[[2013,1,15]],"date-time":"2013-01-15T21:07:54Z","timestamp":1358284074000},"page":"1-15","source":"Crossref","is-referenced-by-count":0,"title":["Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals"],"prefix":"10.1155","volume":"2013","author":[{"given":"Shadi","family":"Traboulsi","sequence":"first","affiliation":[{"name":"Institute for Integrated Systems, Ruhr-Universit\u00e4t Bochum, 44780 Bochum, Germany"}]},{"given":"Valerio","family":"Frascolla","sequence":"additional","affiliation":[{"name":"Institute for Integrated Systems, Ruhr-Universit\u00e4t Bochum, 44780 Bochum, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5362-638X","authenticated-orcid":true,"given":"Nils","family":"Pohl","sequence":"additional","affiliation":[{"name":"Institute for Integrated Systems, Ruhr-Universit\u00e4t Bochum, 44780 Bochum, Germany"}]},{"given":"Josef","family":"Hausner","sequence":"additional","affiliation":[{"name":"Institute for Integrated Systems, Ruhr-Universit\u00e4t Bochum, 44780 Bochum, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7157-6432","authenticated-orcid":true,"given":"Attila","family":"Bilgic","sequence":"additional","affiliation":[{"name":"Institute for Integrated Systems, Ruhr-Universit\u00e4t Bochum, 44780 Bochum, Germany"}]}],"member":"311","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.4018\/jertcs.2010100102"},{"issue":"7","key":"8","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1109\/MC.2008.209","volume":"41","year":"2008","journal-title":"Computer"},{"year":"2009","key":"9"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/56976"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-007-0158-2"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2005.852887"},{"key":"40","doi-asserted-by":"publisher","DOI":"10.1145\/1108956.1108957"},{"key":"42","first-page":"71","volume":"38","year":"2005","journal-title":"Computer"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2013\/369627.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2013\/369627.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2013\/369627.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,10]],"date-time":"2020-12-10T12:42:27Z","timestamp":1607604147000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2013\/369627\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1,15]]},"references-count":8,"alternative-id":["369627","369627"],"URL":"https:\/\/doi.org\/10.1155\/2013\/369627","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2013,1,15]]}}}