{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,19]],"date-time":"2026-04-19T03:28:29Z","timestamp":1776569309466,"version":"3.51.2"},"reference-count":19,"publisher":"Wiley","license":[{"start":{"date-parts":[[2013,5,9]],"date-time":"2013-05-09T00:00:00Z","timestamp":1368057600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2013,5,9]]},"abstract":"<jats:p>An energy efficient low-density parity-check\n(LDPC) decoder using an adaptive wordwidth datapath is presented. \nThe decoder switches between a <jats:italic>Normal Mode<\/jats:italic> and a reduced wordwidth <jats:italic>Low Power Mode<\/jats:italic>. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different <jats:italic>Low Power Mode<\/jats:italic> algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65\u2009nm CMOS. A 5.10\u2009mm<jats:sup>2<\/jats:sup> low power decoder implementation achieves 85.7\u2009Gbps while operating at 185\u2009MHz and dissipates 16.4\u2009pJ\/bit at 1.3\u2009V with early termination. At 0.6\u2009V the decoder throughput is 9.3\u2009Gbps (greater than 6.4\u2009Gbps required for 10GBASE-T) while dissipating an average power of 31\u2009mW. This is 4.6 lower than the state of the art reported power with an SNR loss of 0.35\u2009dB at .<\/jats:p>","DOI":"10.1155\/2013\/913018","type":"journal-article","created":{"date-parts":[[2013,5,9]],"date-time":"2013-05-09T21:04:05Z","timestamp":1368133445000},"page":"1-14","source":"Crossref","is-referenced-by-count":7,"title":["LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization"],"prefix":"10.1155","volume":"2013","author":[{"given":"Tinoosh","family":"Mohsenin","sequence":"first","affiliation":[{"name":"CSEE Department, University of Maryland, Baltimore County, MD 21250, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0488-5283","authenticated-orcid":true,"given":"Houshmand","family":"Shirani-mehr","sequence":"additional","affiliation":[{"name":"ECE Department, University of California, Davis, MD 95616, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bevan M.","family":"Baas","sequence":"additional","affiliation":[{"name":"ECE Department, University of California, Davis, MD 95616, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","reference":[{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1327512.1327513"},{"issue":"1","key":"9","doi-asserted-by":"crossref","first-page":"21","DOI":"10.1109\/TIT.1962.1057683","volume":"8","year":"1962","journal-title":"IRE Transactions on Information Theory"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.925402"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2046957"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042255"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2011360"},{"key":"17","doi-asserted-by":"crossref","first-page":"329","DOI":"10.1007\/s11265-010-0456-y","volume":"61","year":"2010","journal-title":"Journal of Signal Processing Systems"},{"issue":"5","key":"18","doi-asserted-by":"crossref","first-page":"740","DOI":"10.1109\/4.841502","volume":"35","year":"2000","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"2","key":"19","doi-asserted-by":"crossref","first-page":"399","DOI":"10.1109\/18.748992","volume":"45","year":"1999","journal-title":"IEEE Transactions on Information Theory"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/26.768759"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/26.990903"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/LCOMM.2003.814716"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.916606"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/TCOMM.2005.852852"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.926995"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2046964"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864133"},{"issue":"4","key":"34","doi-asserted-by":"crossref","first-page":"1130","DOI":"10.1109\/JSSC.2009.2013772","volume":"44","year":"2009","journal-title":"IEEE Journal of Solid-State Circuits"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2013\/913018.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2013\/913018.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2013\/913018.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,10]],"date-time":"2020-12-10T17:47:07Z","timestamp":1607622427000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2013\/913018\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5,9]]},"references-count":19,"alternative-id":["913018","913018"],"URL":"https:\/\/doi.org\/10.1155\/2013\/913018","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"value":"1065-514X","type":"print"},{"value":"1563-5171","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,5,9]]}}}