{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,12]],"date-time":"2025-11-12T03:19:12Z","timestamp":1762917552150,"version":"3.37.3"},"reference-count":20,"publisher":"Wiley","license":[{"start":{"date-parts":[[2014,7,10]],"date-time":"2014-07-10T00:00:00Z","timestamp":1404950400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2014,7,10]]},"abstract":"<jats:p>Circuit reliability has become a growing concern in today\u2019s nanoelectronics, which motivates strong research interest over the years in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research.<\/jats:p>","DOI":"10.1155\/2014\/529392","type":"journal-article","created":{"date-parts":[[2014,7,10]],"date-time":"2014-07-10T21:12:02Z","timestamp":1405026722000},"page":"1-12","source":"Crossref","is-referenced-by-count":15,"title":["Gate-Level Circuit Reliability Analysis: A Survey"],"prefix":"10.1155","volume":"2014","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0918-0533","authenticated-orcid":true,"given":"Ran","family":"Xiao","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON, Canada N9B 3P4"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2437-5424","authenticated-orcid":true,"given":"Chunhong","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON, Canada N9B 3P4"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","reference":[{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.276"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2009139"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2008.922856"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2007.891066"},{"first-page":"43","volume-title":"Probabilistic logics and the synthesis of reliable organisms from unreliable components","year":"1956","key":"1"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2002.807393"},{"year":"1979","key":"30"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/1297666.1297674"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2007.915203"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2003167"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2010.07.058"},{"volume-title":"A probabilistic-based design for nanoscale computation","year":"2004","key":"10"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.851290"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2008.2010905"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.851289"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2010.07.154"},{"issue":"5","key":"19","first-page":"1009","volume":"10","year":"2011","journal-title":"IEEE Transactions on Nanotechnology"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2012530"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/43.137524"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2014\/529392.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2014\/529392.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2014\/529392.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,9]],"date-time":"2020-12-09T17:27:40Z","timestamp":1607534860000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2014\/529392\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7,10]]},"references-count":20,"alternative-id":["529392","529392"],"URL":"https:\/\/doi.org\/10.1155\/2014\/529392","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2014,7,10]]}}}