{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T11:05:10Z","timestamp":1740135910501,"version":"3.37.3"},"reference-count":12,"publisher":"Wiley","license":[{"start":{"date-parts":[[2014,5,13]],"date-time":"2014-05-13T00:00:00Z","timestamp":1399939200000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2014,5,13]]},"abstract":"<jats:p>This paper describes an embedded FFT processor where the higher radices butterflies maintain one complex multiplier in its critical path. Based on the concept of a radix-<jats:italic>r<\/jats:italic> fast Fourier factorization and based on the FFT parallel processing, we introduce a new concept of a radix-<jats:italic>r<\/jats:italic> Fast Fourier Transform in which the concept of the radix-<jats:italic>r<\/jats:italic> butterfly computation\nhas been formulated as the combination of radix-2<jats:sup><jats:italic>\u03b1<\/jats:italic><\/jats:sup>\/4<jats:sup><jats:italic>\u03b2<\/jats:italic><\/jats:sup> butterflies implemented in parallel. By doing so, the VLSI butterfly implementation for higher radices would be feasible since it maintains approximately the same complexity of the radix-2\/4 butterfly which is obtained by block building of the radix-2\/4 modules. The block building process is achieved by duplicating the block circuit diagram of the radix-2\/4 module that is materialized by means of a feed-back network which will reuse the block circuit diagram of the radix-2\/4 module.<\/jats:p>","DOI":"10.1155\/2014\/690594","type":"journal-article","created":{"date-parts":[[2014,5,13]],"date-time":"2014-05-13T21:19:36Z","timestamp":1400015976000},"page":"1-13","source":"Crossref","is-referenced-by-count":1,"title":["Radix-2<sup><i>\u03b1<\/i><\/sup>\/4<sup><i>\u03b2<\/i><\/sup> Building Blocks for Efficient VLSI\u2019s Higher Radices Butterflies Implementation"],"prefix":"10.1155","volume":"2014","author":[{"given":"Marwan A.","family":"Jaber","sequence":"first","affiliation":[{"name":"Laboratory of Signals and Systems Integrations, Electrical and Computer Engineering Department, Universit\u00e9 du Qu\u00e9bec \u00e0 Trois-Rivi\u00e8res, QC, Canada G9A 5H7"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7807-7919","authenticated-orcid":true,"given":"Daniel","family":"Massicotte","sequence":"additional","affiliation":[{"name":"Laboratory of Signals and Systems Integrations, Electrical and Computer Engineering Department, Universit\u00e9 du Qu\u00e9bec \u00e0 Trois-Rivi\u00e8res, QC, Canada G9A 5H7"}]}],"member":"311","reference":[{"key":"1","doi-asserted-by":"crossref","first-page":"297","DOI":"10.1090\/S0025-5718-1965-0178586-1","volume":"19","year":"1965","journal-title":"Mathematics of Computation"},{"issue":"1","key":"2","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1049\/el:19840012","volume":"20","year":"1984","journal-title":"Electronics Letters"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1073\/pnas.73.4.1005"},{"year":"1997","series-title":"Linkoping Studies in Science and Technology no. 619","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2007.892722"},{"issue":"5","key":"12","doi-asserted-by":"crossref","first-page":"702","DOI":"10.1109\/JSSC.1984.1052211","volume":"19","year":"1984","journal-title":"IEEE Journal of Solid-State Circuits"},{"year":"1978","series-title":"Applications of Digital Signal Processing to Radar","key":"13"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2178275"},{"issue":"6","key":"17","first-page":"564","volume":"130","year":"1983","journal-title":"IEE Proceedings F: Communications, Radar and Signal Processing"},{"issue":"5","key":"18","first-page":"414","volume":"33","year":"1984","journal-title":"IEEE Transactions on Computers"},{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2048373"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2011.2168525"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2014\/690594.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2014\/690594.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2014\/690594.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,9]],"date-time":"2020-12-09T19:28:27Z","timestamp":1607542107000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2014\/690594\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5,13]]},"references-count":12,"alternative-id":["690594","690594"],"URL":"https:\/\/doi.org\/10.1155\/2014\/690594","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2014,5,13]]}}}