{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,8]],"date-time":"2026-09-08T15:01:48Z","timestamp":1788879708621,"version":"build-2803163510"},"reference-count":20,"publisher":"Wiley","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electrical and Computer Engineering"],"published-print":{"date-parts":[[2014]]},"abstract":"<jats:p>This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES (advanced encryption standard) Key Expander and Round Function, which offer increased side-channel attack (SCA) resistance. These designs are based on a delay-insensitive (DI) logic paradigm known as null convention logic (NCL), which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR) ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output) analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach.<\/jats:p>","DOI":"10.1155\/2014\/837572","type":"journal-article","created":{"date-parts":[[2014,7,20]],"date-time":"2014-07-20T17:06:54Z","timestamp":1405876014000},"page":"1-13","source":"Crossref","is-referenced-by-count":16,"title":["Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance"],"prefix":"10.1155","volume":"2014","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4998-9131","authenticated-orcid":true,"given":"Siva","family":"Kotipalli","sequence":"first","affiliation":[{"name":"Samsung Electronics, Austin, TX 78754, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7014-5630","authenticated-orcid":true,"given":"Yong-Bin","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9104-0563","authenticated-orcid":true,"given":"Minsu","family":"Choi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Missouri University of Science & Technology, Rolla, MO 65409, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"311","reference":[{"key":"1","year":"2001"},{"key":"2","first-page":"2004","volume":"66","year":"2004","journal-title":"ACR Eprint Archive, Report"},{"key":"6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1007\/978-3-642-10838-9_6","volume-title":"Mechanism behind information leakage in electromagnetic analysis of cryptographic modules","volume":"5932","year":"2009"},{"key":"7","first-page":"388","volume-title":"Differential power analysis","year":"1999"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1004593"},{"key":"9","first-page":"173","volume-title":"IPA: a new class of power attacks","year":"1999"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/4.933467"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.2200\/S00202ED1V01Y200907DCS023"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1004593"},{"key":"15","volume":"31","year":"2007"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.250627"},{"key":"24","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"415","DOI":"10.1007\/3-540-36400-5_30","volume-title":"True random number generator embedded in reconfigurable hardware","volume":"2523","year":"2003"},{"key":"25","first-page":"450","volume-title":"A hardware random number generator","year":"2003"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1190581"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/81.847868"},{"key":"28","year":"1999"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1016\/S0378-4754(98)00078-0"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45238-6_14"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36400-5_14"},{"key":"36","year":"2006"}],"container-title":["Journal of Electrical and Computer Engineering"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2014\/837572.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2014\/837572.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2014\/837572.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T13:01:55Z","timestamp":1498136515000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.hindawi.com\/journals\/jece\/2014\/837572\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014]]},"references-count":20,"alternative-id":["837572","837572"],"URL":"https:\/\/doi.org\/10.1155\/2014\/837572","relation":{},"ISSN":["2090-0147","2090-0155"],"issn-type":[{"value":"2090-0147","type":"print"},{"value":"2090-0155","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014]]}}}