{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,12]],"date-time":"2025-11-12T03:18:42Z","timestamp":1762917522055,"version":"3.37.3"},"reference-count":13,"publisher":"Wiley","license":[{"start":{"date-parts":[[2014,7,7]],"date-time":"2014-07-07T00:00:00Z","timestamp":1404691200000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["VLSI Design"],"published-print":{"date-parts":[[2014,7,7]]},"abstract":"<jats:p>This paper presents a new multioutput and high throughput pseudorandom number generator. The scheme is to make the homogenized Logistic chaotic sequence as unified hyperchaotic system parameter. So the unified hyperchaos can transfer in different chaotic systems and the output can be more complex with the changing of homogenized Logistic chaotic output. Through processing the unified hyperchaotic 4-way outputs, the output will be extended to 26 channels. In addition, the generated pseudorandom sequences have all passed NIST SP800-22 standard test and DIEHARD test. The system is designed in Verilog HDL and experimentally verified on a Xilinx Spartan 6 FPGA for a maximum throughput of 16.91\u2009Gbits\/s for the native chaotic output and 13.49\u2009Gbits\/s for the resulting pseudorandom number generators.<\/jats:p>","DOI":"10.1155\/2014\/923618","type":"journal-article","created":{"date-parts":[[2014,7,7]],"date-time":"2014-07-07T21:08:11Z","timestamp":1404767291000},"page":"1-9","source":"Crossref","is-referenced-by-count":5,"title":["High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos"],"prefix":"10.1155","volume":"2014","author":[{"given":"Kaiyu","family":"Wang","sequence":"first","affiliation":[{"name":"Department of Electronic Engineering, Dalian University of Technology, Gaoxinyuanqu Linggong Road 2, Dalian 116024, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6486-2262","authenticated-orcid":true,"given":"Qingxin","family":"Yan","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Dalian University of Technology, Gaoxinyuanqu Linggong Road 2, Dalian 116024, China"}]},{"given":"Shihua","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Computer Science and Technology, Hulunbuir College, Xuefu Road, Hulunbuir 021008, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7333-6072","authenticated-orcid":true,"given":"Xianwei","family":"Qi","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Dalian University of Technology, Gaoxinyuanqu Linggong Road 2, Dalian 116024, China"}]},{"given":"Yudi","family":"Zhou","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Dalian University of Technology, Gaoxinyuanqu Linggong Road 2, Dalian 116024, China"}]},{"given":"Zhenan","family":"Tang","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Dalian University of Technology, Gaoxinyuanqu Linggong Road 2, Dalian 116024, China"}]}],"member":"311","reference":[{"issue":"11","key":"1","first-page":"64","volume":"35","year":"2012","journal-title":"Modern Electronics Technique"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1016\/j.physleta.2005.09.060"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1016\/j.physleta.2008.04.002"},{"issue":"2","key":"6","first-page":"31","volume":"32","year":"2000","journal-title":"Journal of Northeast Normal University (Natural Science Edition)"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2013.06.007"},{"issue":"6","key":"8","first-page":"725","volume":"25","year":"2010","journal-title":"Journal of Systems Engineering"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1142\/S021812740200631X"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1142\/S0217979211057967"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1007\/s11235-011-9460-1"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.892399"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.13.0112.0677"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2083170"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1142\/S0218127410028136"}],"container-title":["VLSI Design"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/archive\/2014\/923618.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2014\/923618.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/archive\/2014\/923618.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,12,9]],"date-time":"2020-12-09T21:33:05Z","timestamp":1607549585000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.hindawi.com\/journals\/vlsi\/2014\/923618\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7,7]]},"references-count":13,"alternative-id":["923618","923618"],"URL":"https:\/\/doi.org\/10.1155\/2014\/923618","relation":{},"ISSN":["1065-514X","1563-5171"],"issn-type":[{"type":"print","value":"1065-514X"},{"type":"electronic","value":"1563-5171"}],"subject":[],"published":{"date-parts":[[2014,7,7]]}}}