{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T17:18:39Z","timestamp":1740158319767,"version":"3.37.3"},"reference-count":7,"publisher":"Wiley","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61170083","60873016","20114307110001","2009AAOIZ102"],"award-info":[{"award-number":["61170083","60873016","20114307110001","2009AAOIZ102"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61170083","60873016","20114307110001","2009AAOIZ102"],"award-info":[{"award-number":["61170083","60873016","20114307110001","2009AAOIZ102"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Doctor Program Foundation of Education Ministry of China","award":["61170083","60873016","20114307110001","2009AAOIZ102"],"award-info":[{"award-number":["61170083","60873016","20114307110001","2009AAOIZ102"]}]},{"name":"National High Technology Research and Development Program of China","award":["61170083","60873016","20114307110001","2009AAOIZ102"],"award-info":[{"award-number":["61170083","60873016","20114307110001","2009AAOIZ102"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Electrical and Computer Engineering"],"published-print":{"date-parts":[[2015]]},"abstract":"<jats:p>Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh\/torus network consumes 15.2%\/18.9% more power on average, whereas it can averagely obtain 45.0%\/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.<\/jats:p>","DOI":"10.1155\/2015\/862387","type":"journal-article","created":{"date-parts":[[2015,8,16]],"date-time":"2015-08-16T17:02:20Z","timestamp":1439744540000},"page":"1-16","source":"Crossref","is-referenced-by-count":1,"title":["Applying Partial Power-Gating to Direction-Sliced Network-on-Chip"],"prefix":"10.1155","volume":"2015","author":[{"given":"Feng","family":"Wang","sequence":"first","affiliation":[{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, China"}]},{"given":"Xiantuo","family":"Tang","sequence":"additional","affiliation":[{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, China"}]},{"given":"Zuocheng","family":"Xing","sequence":"additional","affiliation":[{"name":"National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha 410073, China"}]}],"member":"311","reference":[{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2007.4378783"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2011.2111270"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1587\/transinf.e95.d.1519"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1049\/el.2013.3225"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110470"},{"year":"2004","series-title":"The Morgan Kaufmann Series in Computer Architecture and Design","key":"15"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/81.841927"}],"container-title":["Journal of Electrical and Computer Engineering"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2015\/862387.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2015\/862387.xml","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/downloads.hindawi.com\/journals\/jece\/2015\/862387.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,7,27]],"date-time":"2016-07-27T16:21:26Z","timestamp":1469636486000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.hindawi.com\/journals\/jece\/2015\/862387\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015]]},"references-count":7,"alternative-id":["862387","862387"],"URL":"https:\/\/doi.org\/10.1155\/2015\/862387","relation":{},"ISSN":["2090-0147","2090-0155"],"issn-type":[{"type":"print","value":"2090-0147"},{"type":"electronic","value":"2090-0155"}],"subject":[],"published":{"date-parts":[[2015]]}}}